參數(shù)資料
型號： AD9613BCPZRL7-170
廠商： Analog Devices Inc
文件頁數(shù)： 12/36頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 170MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 738mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個差分，雙極
AD9613
Data Sheet
Rev. C | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADC DC Specifications............................................................... 3
ADC AC Specifications ............................................................... 4
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 11
Thermal Characteristics ............................................................ 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 16
Equivalent Circuits ......................................................................... 22
Theory of Operation ...................................................................... 23
ADC Architecture ...................................................................... 23
Analog Input Considerations ................................................... 23
Voltage Reference ....................................................................... 25
Clock Input Considerations...................................................... 25
Power Dissipation and Standby Mode .................................... 27
Digital Outputs ........................................................................... 27
ADC Overrange (OR)................................................................ 27
Channel/Chip Synchronization.................................................... 28
Serial Port Interface (SPI).............................................................. 29
Configuration Using the SPI..................................................... 29
Hardware Interface..................................................................... 29
SPI Accessible Features.............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table............................... 31
Memory Map Register Table..................................................... 32
Memory Map Register Description ......................................... 34
Applications Information .............................................................. 35
Design Guidelines ...................................................................... 35
Outline Dimensions....................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
1/13—Rev. B to Rev. C
Changes to Features...........................................................................1
Changes to Table 1.............................................................................3
Changes to Table 2 ............................................................................5
Change to Logic Inputs (SDIO) Paramter, Table 3........................6
Changes to Table 4.............................................................................8
Change to Reading the Memory Map Register Table Section........31
Changes to Table 14.........................................................................33
Change to Memory Map Register Description Section..............34
Updated Outline Dimensions........................................................36
9/11—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
Changes to Temperature Drift Parameters ................................... 3
Changes Output Offset Voltage (VOS), ANSI Mode Typ
Parameter and Output Offset Voltage (VOS), Reduced Swing
Mode Parameter................................................................................ 7
Changes DCO to Data Skew (tSKEW) Parameters .......................... 8
Changes to Output Enable Bar and Power-Down Pin Type
and Pin 47 Description .................................................................. 13
Changes to Figure 5 and Pin 7 and Pin 8 Descriptions............. 14
Changes to Pin 42 and Pin 43, Output Enable Bar and Power-
Down Pin Type, and Pin 47 Descriptions................................... 15
Changes to Typical Performance Characteristics Conditions.. 16
Changes to Fiugre 43...................................................................... 22
Added ADC Overrange (OR) Section......................................... 27
Changes to Channel/Chip Synchronization Section ................. 28
Changes to Reading the Memory Map Register Table
Section and Transfer Register Map Section ................................ 31
Changes to Register 0x02, Bits[5:4].............................................. 32
Changes to Register 0x16, Bit 5 .................................................... 33
Added Register 0x3A ..................................................................... 34
Deleted Register 0x59 .................................................................... 34
Changes to Bit 0—Master Sync Buffer Enable Section ............. 34
Deleted SYNC Pin Control (Register 0x59) Section.................. 34
5/11—Rev. 0 to Rev. A
Changes to Table 2, AD9613-170: Worst Second or Third
Harmonic and Worst Other (Harmonic or Spur) Max Values
and Spurious Free Dynamic Range Min Value .............................4
4/11—Revision 0: Initial Version
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