參數(shù)資料
型號(hào): AD9613BCPZRL7-170
廠商: Analog Devices Inc
文件頁數(shù): 5/36頁
文件大小: 0K
描述: IC ADC 12BIT SRL 170MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 12
采樣率(每秒): 170M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 738mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,雙極
Data Sheet
AD9613
Rev. C | Page 13 of 36
Pin No.
Mnemonic
Type
Description
Digital Outputs
14
D0+ (LSB)
Output
Channel A/Channel B LVDS Output Data 0—True.
13
D0 (LSB)
Output
Channel A/Channel B LVDS Output Data 0—Complement.
16
D1+
Output
Channel A/Channel B LVDS Output Data 1—True.
15
D1
Output
Channel A/Channel B LVDS Output Data 1—Complement.
18
D2+
Output
Channel A/Channel B LVDS Output Data 2—True.
17
D2
Output
Channel A/Channel B LVDS Output Data 2—Complement.
21
D3+
Output
Channel A/Channel B LVDS Output Data 3—True.
20
D3
Output
Channel A/Channel B LVDS Output Data 3—Complement.
23
D4+
Output
Channel A/Channel B LVDS Output Data 4—True.
22
D4
Output
Channel A/Channel B LVDS Output Data 4—Complement.
27
D5+
Output
Channel A/Channel B LVDS Output Data 5—True.
26
D5
Output
Channel A/Channel B LVDS Output Data 5—Complement.
30
D6+
Output
Channel A/Channel B LVDS Output Data 6—True.
29
D6
Output
Channel A/Channel B LVDS Output Data 6—Complement.
32
D7+
Output
Channel A/Channel B LVDS Output Data 7—True.
31
D7
Output
Channel A/Channel B LVDS Output Data 7—Complement.
34
D8+
Output
Channel A/Channel B LVDS Output Data 8—True.
33
D8
Output
Channel A/Channel B LVDS Output Data 8—Complement.
36
D9+
Output
Channel A/Channel B LVDS Output Data 9—True.
35
D9
Output
Channel A/Channel B LVDS Output Data 9—Complement.
39
D10+
Output
Channel A/Channel B LVDS Output Data 10—True.
38
D10
Output
Channel A/Channel B LVDS Output Data 10—Complement.
41
D11+ (MSB)
Output
Channel A/Channel B LVDS Output Data 11—True.
40
D11 (MSB)
Output
Channel A/Channel B LVDS Output Data 11—Complement.
43
OR+
Output
Channel A/Channel B LVDS Overrange—True.
42
OR
Output
Channel A/Channel B LVDS Overrange—Complement.
25
DCO+
Output
Channel A/Channel B LVDS Data Clock Output—True.
24
DCO
Output
Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
45
SCLK
Input
SPI Serial Clock.
44
SDIO
Input/Output
SPI Serial Data I/O.
46
CSB
Input
SPI Chip Select (Active Low).
Output Enable Bar and
Power-Down
47
OEB
Input/Output
Output Enable Bar Input (Active Low).
48
PDWN
Input/Output
Power-Down Input (Active High). Operation depends upon SPI mode;
this input can be configured as power-down or standby. For further
description, refer to Table 14.
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