參數(shù)資料
型號(hào)： AD9613BCPZRL7-170
廠商： Analog Devices Inc
文件頁數(shù)： 26/36頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 170MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 738mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)差分，雙極
AD9613
Data Sheet
Rev. C | Page 32 of 36
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 14 are not currently supported for this device.
Table 14. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00
SPI port
configuration
(global)1
0
LSB first
Soft reset
1
Soft reset
LSB first
0
0x18
The nibbles
are mirrored
so that LSB-
first mode
or MSB-first
mode
registers
correctly,
regardless
of shift
mode
0x01
Chip ID
(global)
8-bit chip ID[7:0] (AD9613 = 0x83)
(default)
0x83
Read only
0x02
Chip grade
(global)
Open
Speed grade ID
00 = 250 MSPS
01 = 210 MSPS
11 = 170 MSPS
Open
Speed
grade ID
used to
differentiate
devices;
read only
Channel Index and Transfer Registers
0x05
Channel index
(global)
Open
ADC B
(default)
ADC A
(default)
0x03
Bits are set
to
determine
which
device on
the chip
receives the
next write
command;
applies to
local
registers
only
0xFF
Transfer
(global)
Open
Transfer
0x00
Synchron-
ously
transfers
data from
the master
shift register
to the slave
ADC Functions
0x08
Power modes
(local)
Open
External
power-
downpin
function
(local)
0 = power-
down
1=standby
Open
Internal power-down mode
(local)
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
0x00
Determines
various
generic
modes of
chip
operation
0x09
Global clock
(global)
Open
Duty cycle
stabilizer
(default)
0x01
0x0B
Clock divide
(global)
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
Clock divide
values other
than 000
auto-
matically
cause the
duty cycle
stabilizer to
become
active
相關(guān)PDF資料
PDF描述
IDT72225LB25PFI IC FIFO 1024X18 SYNC 25NS 64TQFP
LT1138ACSW#TR IC TXRX 5V RS232 LP CAPS 28SOIC
IDT72V241L20J IC FIFO SYNC 4KX9 20NS 32PLCC
LT1130ACSW#TRPBF IC 5DRV/5RCV RS232 5V 28-SOIC
IDT72V231L15J IC FIFO SYNC 2048X9 15NS 32-PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9613BCPZRL7-210 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12 Bit 210Msps Dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9613BCPZRL7-250 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12 Bit 250Msps Dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9615BH 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD9615TH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current-Feedback Operational Amplifier
AD9617 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Distortion, Precision, Wide Bandwidth Op Amp
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*