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參數(shù)資料
| 型號(hào)： | AD9627-125EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 28/76頁(yè) |
| 文件大小： | 0K |
| 描述： | IC A/D 12BIT 125MSPS DL EVAL BRD |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 900mW @ 125MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9627 |
| 已供物品： | 板，電源 |
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AD9627
Rev. B | Page 34 of 76
When the fast detect mode select bits are set to 0b001, 0b010, or
0b011, a subset of the fast detect output pins is available. In these
modes, the fast detect output pins have a latency of six clock cycles.
Table 19 shows the corresponding ADC input levels when the
fast detect mode select bits are set to 0b001 (that is, when ADC fast
magnitude is presented on the FD[3:1] pins).
Table 19. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 001
ADC Fast Magnitude
on FD[3:1] Pins
Nominal Input
Magnitude
Below FS (dB)
Nominal Input
Magnitude
Uncertainty (dB)
000
<24
Minimum to 18.07
001
24 to 14.5
30.14 to 12.04
010
14.5 to 10
18.07 to 8.52
011
10 to 7
12.04 to 6.02
100
7 to 5
8.52 to 4.08
101
5 to 3.25
6.02 to 2.5
110
3.25 to 1.8
4.08 to 1.16
111
1.8 to 0
2.5 to 0
When the fast detect mode select bits are set to 0b010 or 0b011
(that is, when ADC fast magnitude is presented on the FD[3:2]
pins), the LSB is not provided. The input ranges for this mode
are shown in Table 20.
Table 20. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 010 or 011
ADC Fast
Magnitude on
FD[2:1] Pins
Nominal Input
Magnitude
Below FS (dB)
Nominal Input
Magnitude
Uncertainty (dB)
00
<14.5
Minimum to 12.04
01
14.5 to 7
18.07 to 6.02
10
7 to 3.25
8.52 to 2.5
11
3.25 to 0
4.08 to 0
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 12 ADC clock cycles. An overrange at the
input is indicated by this bit 12 clock cycles after it occurs.
GAIN SWITCHING
The AD9627 includes circuitry that is useful in applications either
where large dynamic ranges exist or where gain ranging converters
are employed. This circuitry allows digital thresholds to be set
such that an upper threshold and a lower threshold can be
programmed. Fast detect mode select bit = 010 through fast
detect mode select bit = 101 support various combinations of the
gain switching options.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Coarse Upper Threshold (C_UT)
The coarse upper threshold indicator is asserted if the ADC fast
magnitude input level is greater than the level programmed in
the coarse upper threshold register (Address 0x105[2:0]). This
value is compared with the ADC Fast Magnitude Bits[2:0]. The
coarse upper threshold output is output two clock cycles after the
level is exceeded at the input and, therefore, it provides a fast
indication of the input signal level. The coarse upper threshold
levels are shown in Table 21. This indicator remains asserted for
a minimum of two ADC clock cycles or until the signal drops
below the threshold level.
Table 21. Coarse Upper Threshold Levels
Coarse Upper Threshold
Register 0x105[2:0]
C_UT Is Active When Signal
Magnitude Below FS
Is Greater Than (dB)
000
<24
001
24
010
14.5
011
10
100
7
101
5
110
3.25
111
1.8
Fine Upper Threshold (F_UT)
The fine upper threshold indicator is asserted if the input
magnitude exceeds the value programmed in the fine upper
threshold register located in Register 0x106 and Register 0x107.
The 13-bit threshold register is compared with the signal magni-
tude at the output of the ADC. This comparison is subject to the
ADC clock latency but is accurate in terms of the converter
resolution. The fine upper threshold magnitude is defined by
the following equation:
dBFS = 20 log(Threshold Magnitude/213)
Fine Lower Threshold (F_LT)
The fine lower threshold indicator is asserted if the input
magnitude is less than the value programmed in the fine lower
threshold register located at Register 0x108 and Register 0x109.
The fine lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to ADC clock latency but is accurate
in terms of the converter resolution. The fine lower threshold
magnitude is defined by the following equation:
dBFS = 20 log(Threshold Magnitude/213)
The operation of the fine upper threshold indicators and fine
lower threshold indicators is shown in Figure 67.
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