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參數(shù)資料
| 型號(hào)： | AD9627-125EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D 12BIT 125MSPS DL EVAL BRD |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 900mW @ 125MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9627 |
| 已供物品： | 板，電源 |
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AD9627
Rev. B | Page 32 of 76
DIGITAL OUTPUTS
The AD9627 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families by matching DRVDD to the
digital supply of the interfaced logic. The AD9627 can also be
configured for LVDS outputs using a DRVDD supply voltage
of 1.8 V.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 15).
As detailed in Application Note AN-877, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 15. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
SCLK/DFS
SDIO/DCS
AGND (default)
Offset binary
DCS disabled
AVDD
Twos complement
DCS enabled
Digital Output Enable Function (OEB)
The AD9627 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the SMI SDO/OEB
pin or through the SPI interface. If the SMI SDO/OEB pin is low,
the output data drivers are enabled. If the SMI SDO/OEB pin is
high, the output data drivers are placed in a high impedance state.
This OEB function is not intended for rapid access to the data
bus. Note that OEB is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data and fast detect outputs
of each channel can be independently three-stated by using the
output enable bar bit in Register 0x14.
TIMING
The AD9627 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9627.
These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9627 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9627 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO, unless the DCO clock
polarity has been changed via the SPI. See Figure 2 and Figure 3
for a graphical timing description.
Table 16. Output Data Format
Input (V)
Condition (V)
Offset Binary Output Mode
Twos Complement Mode
OR
VIN+ VIN
< VREF 0.5 LSB
0000 0000 0000
1000 0000 0000
1
VIN+ VIN
= VREF
0000 0000 0000
1000 0000 0000
0
VIN+ VIN
= 0
1000 0000 0000
0000 0000 0000
0
VIN+ VIN
= +VREF 1.0 LSB
1111 1111 1111
0111 1111 1111
0
VIN+ VIN
> +VREF 0.5 LSB
1111 1111 1111
0111 1111 1111
1
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