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參數(shù)資料
| 型號： | AD9627-125EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/76頁 |
| 文件大小： | 0K |
| 描述： | IC A/D 12BIT 125MSPS DL EVAL BRD |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標準）： | 900mW @ 125MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9627 |
| 已供物品： | 板，電源 |
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AD9627
Rev. B | Page 38 of 76
DC Correction Bandwidth
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).
The bandwidth is controlled by writing the 4-bit dc correction
register located at Register 0x10C, Bits[5:2].
The following equation can be used to compute the bandwidth
value for the dc correction circuit:
2
_
14
CLK
k
f
BW
Corr
DC
where:
k is the 4 bit value programmed in Register 0x10C, Bits[5:2]
(values between 0 and 13 are valid for k; programming 14 or
15 provides the same result as programming 13).
fCLK is the AD9627 ADC sample rate in hertz (Hz).
DC Correction Readback
The current dc correction value can be read back in Register 0x10D
and Register 0x10E for Channel A and Register 0x10F and
Register 0x110 for Channel B. The dc correction value is a 12-bit
value that can span the entire input range of the ADC.
DC Correction Freeze
Setting Bit 6 of Register 0x10C freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
DC Correction Enable Bits
Setting Bit 0 of Register 0x10C enables dc correction for use in
the signal monitor calculations. The calculated dc correction
value can be added to the output data signal path by setting Bit 1
of Register 0x10C.
SIGNAL MONITOR SPORT OUTPUT
The SPORT is a serial interface with three output pins:
SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and
SMI SDO (SPORT data output). The SPORT is the master and
drives all three SPORT output pins on the chip.
SMI SCLK
The data and frame sync are driven on the positive edge of the
SMI SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4,
or 1/8 the ADC clock rate, based on the SPORT controls. The SMI
SCLK can also be gated off when not sending any data, based on
the SPORT SMI SCLK sleep bit. Using this bit to disable the SMI
SCLK when it is not needed can reduce any coupling errors back
into the signal path, if these prove to be a problem in the system.
Doing so, however, has the disadvantage of spreading the frequency
content of the clock. If desired, the SMI SCLK can be left running
to ease frequency planning.
SMI SDFS
The SMI SDFS is the serial data frame sync, and it defines the
start of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
SMI SDO
The SMI SDO is the serial data output of the block. The data
is sent MSB first on the next positive edge after the SMI SDFS.
Each data output block includes one or more rms magnitude, peak
level, and threshold crossing values from each datapath in the
stated order. If enabled, the data is sent, rms first, followed by peak
and threshold, as shown in Figure 71.
20 CYCLES
16 CYCLES
20 CYCLES
16 CYCLES
SMI SDFS
MSB
RMS/MS CH A
PK CH A
PK CH B
THR CH B
RMS/MS CH B
RMS/MS CH A
LSB
THR CH A
SMI SDO
SMI SCLK
GATED, BASED ON CONTROL
06
57
1-
07
1
Figure 71. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)
20 CYCLES
16 CYCLES
20 CYCLES
16 CYCLES
SMI SCLK
SMI SDFS
SMI SDO
MSB
RMS/MS CH A
LSB
THR CH A
RMS/MS CH B LSB
THR CH B
GATED, BASED ON CONTROL
06
57
1-
07
2
Figure 72. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)
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