參數(shù)資料
型號： AD9707BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 29/44頁
文件大小： 0K
描述： IC DAC TX 14BIT 175MSPS 32-LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
設(shè)置時間： 11ns
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 50mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 175M
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
Data Sheet
AD9704/AD9705/AD9706/AD9707
Rev. B | Page 35 of 44
DAC TRANSFER FUNCTION
The AD9704/AD9705/AD9706/AD9707 provide complementary
current outputs, IOUTA and IOUTB. IOUTA provides a near
full-scale current output, IOUTFS, when all bits are high (that is,
DAC CODE = 2N 1, where N = 8, 10, 12, or 14 for the AD9704,
AD9705, AD9706, and AD9707, respectively), while IOUTB, the
complementary output, provides no current. The current output
appearing at IOUTA and IOUTB is a function of both the input
code and IOUTFS and can be expressed as
IOUTA = (DAC CODE/2N) × IOUTFS
(1)
IOUTB = ((2N 1) DAC CODE)/2N × IOUTFS
(2)
where DAC CODE = 0 to 2N 1 (that is, decimal representation).
IOUTFS is a function of the reference current, IREF, which is
nominally set by a reference voltage, VREFIO, and an external
resistor, RSET. It can be expressed as
IOUTFS = 32 × IREF
(3)
where
IREF = VREFIO/RSET
(4)
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and
IOUTB should be connected to matching resistive loads (RLOAD)
that are tied to analog common (ACOM). The single-ended
voltage output appearing at the IOUTA and IOUTB nodes is
VIOUTA = IOUTA × RLOAD
(5)
VIOUTB = IOUTB × RLOAD
(6)
To achieve the maximum output compliance of 1 V at the
nominal 2 mA output current, RLOAD must be set to 500 Ω.
Also, the full-scale value of VIOUTA and VIOUTB must not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
VDIFF = (IOUTA – IOUTB) × RLOAD
(7)
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be
expressed as
VDIFF = {(2 × DAC CODE – (2N 1))/2N} ×
(32 × VREFIO/RSET) × RLOAD
(8)
Equation 7 and Equation 8 highlight some of the advantages of
operating the AD9704/AD9705/AD9706/AD9707 differentially.
First, the differential operation helps cancel common-mode error
sources associated with IOUTA and IOUTB, such as noise,
distortion, and dc offsets. Second, the differential code dependent
current and subsequent voltage, VDIFF, is twice the value of the
single-ended voltage output (that is, VIOUTA or VIOUTB), thus
providing twice the signal power to the load.
The gain drift temperature performance for a single-ended
output (VIOUTA and VIOUTB) or the differential output (VDIFF) of
the AD9704/AD9705/AD9706/AD9707 can be enhanced by
selecting temperature tracking resistors for RLOAD and RSET,
because of their ratiometric relationship, as shown in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA, and
IOUTB can be configured for single-ended or differential oper-
ation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VIOUTA and VIOUTB, via a load resistor,
RLOAD, as described in the DAC Transfer Function section by
Equation 5 through Equation 8. The differential voltage, VDIFF,
existing between VIOUTA and VIOUTB, can also be converted to a
single-ended voltage via a transformer or a differential amplifier
configuration. The ac performance of the AD9704/AD9705/
AD9706/AD9707 is optimum and is specified using a differential
transformer-coupled output in which the voltage swing at
IOUTA and IOUTB is limited to ±0.5 V.
The distortion and noise performance of the AD9704/AD9705/
AD9706/AD9707 can be enhanced when it is configured for
differential operation. The common-mode error sources of both
IOUTA and IOUTB can be significantly reduced by the common-
mode rejection of a transformer or differential amplifier. These
common-mode error sources include even-order distortion
products and noise. The enhancement in distortion performance
becomes more significant as the frequency content of the
reconstructed waveform increases and/or its amplitude increases.
This is due to the first-order cancellation of various dynamic
common-mode distortion mechanisms, digital feedthrough,
and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Because the output currents of IOUTA and
IOUTB are complementary, they become additive when
processed differentially.
When the AD9704/AD9705/AD9706/AD9707 is being used at its
nominal operating point of 2 mA output current and 0.5 V output
swing is desired, RLOAD must be set to 250 Ω. A properly selected
transformer allows the AD9704/AD9705/AD9706/ AD9707 to
provide the required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined by
the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 200 MΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, VIOUTA and VIOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration results in the
optimum dc linearity. Note that the INL/DNL specifications for
the AD9704/AD9705/AD9706/AD9707 are measured with IOUTA
maintained at a virtual ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The absolute maximum negative output
compliance range of 1 V is set by the breakdown limits of the
CMOS process. Operation beyond this maximum limit can result
in a breakdown of the output stage and affect the reliability of
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