參數(shù)資料
型號： AD9716BCPZRL7
廠商： Analog Devices Inc
文件頁數(shù)： 33/80頁
文件大?。?/td> 0K
描述： IC DAC DUAL 12BIT LO PWR 40LFCSP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 750
系列： TxDAC®
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 86mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 125M
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 39 of 80
Register
Address
Bit
Name
Description
Memory R/W
0x12
7
CALRSTQ
0 (default): no action.
1: clear CALSTATQ.
6
CALRSTI
0 (default): no action.
1: clear CALSTATI.
4
CALEN
0 (default): no action.
1: initiate device self-calibration.
3
SMEMWR
0 (default): no action.
1: write to static memory (calibration coefficients).
2
SMEMRD
0 (default): no action.
1: read from static memory (calibration coefficients).
1
UNCALQ
0 (default): no action.
1: reset Q DAC calibration coefficients to default (uncalibrated).
0
UNCALI
0 (default): no action.
1: reset I DAC calibration coefficients to default (uncalibrated).
CLKMODE
0x14
7:6
CLKMODEQ[1:0]
Depending on the CLKMODEN bit setting, these two bits reflect the phase
relationship between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
4
Searching
Data path retimer status bit.
0 (default): clock relationship established.
1: indicates that the internal data path retimer is searching for clock relationship
(device output is not usable while this bit is high).
3
Reacquire
Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.
2
CLKMODEN
0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and
read back in CLKMODEI[1:0] and CLKMODEQ[1:0].
1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers.
1:0
CLKMODEI[1:0]
Depending on CLKMODEN bit setting, these two bits reflect the phase
relationship between DCLKIO and CLKIN as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Version
0x1F
7:0
Version[7:0]
Hardware version of the device. This register is set to 0x03 for the latest version of
the device.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9716-DPG2-EBZ 功能描述:ADC 12BIT DUAL 40LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9716-EBZ 制造商:Analog Devices 功能描述:DUAL 12 BIT LOW POWER CONVERTER - Boxed Product (Development Kits) 制造商:Rochester Electronics LLC 功能描述:
AD9717 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters
AD9717BCPZ 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF)
AD9717BCPZ 制造商:Analog Devices 功能描述:IC DAC 14BIT 125MSPS LFCSP-40
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