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參數(shù)資料
| 型號： | AD9716BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 12BIT LO PWR 40LFCSP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 750 |
| 系列： | TxDAC® |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 86mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 125M |
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AD9714/AD9715/AD9716/AD9717
Rev. A | Page 46 of 80
COARSE GAIN ADJUSTMENT
Option 1
A coarse full-scale output current adjustment can be achieved
using the lower six bits in Register 0x0D. This adds or subtracts
up to 20% from the band gap voltage on Pin 34 (REFIO), and
the voltage on the FSADJx resistors tracks this change. As a
result, the DAC full-scale current varies by the same amount.
A secondary effect to changing the REFIO voltage is that the
full-scale voltage in the AUXDAC also changes by the same
magnitude. The register uses twos complement format, in
which 011111 maximizes the voltage on the REFIO node
and 100000 minimizes the voltage.
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0
8
16
24
32
40
48
56
CODE
V
RE
F
07
26
5-
05
4
Figure 98. Typical VREF Voltage vs. Code
Option 2
While using the internal FSADJx resistors, each main DAC can
achieve independently controlled coarse gain using the lower
six bits of Register 0x04 (IRSET[5:0]) and Register 0x07
(QRSET[5:0]). Unlike Coarse Gain Option 1, this impacts only
the main DAC full-scale output current. The register uses twos
complement format and allows the output current to be changed
in approximately 0.25 dB steps.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1020
3040
50
60
xRSET CODE
OU
T
P
U
T
OF
I/V
C
ON
V
E
R
TE
R
(
V
)
0
726
5-
0
55
VOUT_Q OR VOUT_I
Figure 99. Effect of xRSET Code
Option 3
Even when the device is in pin mode, full-scale values can be
adjusted by sourcing or sinking current from the FSADJx pins.
Any noise injected here appears as amplitude modulation of the
output. Thus, a portion of the required series resistance (at least
20 kΩ) must be installed right at the pin. A range of ±10% is
quite practical using this method.
Option 4
As in Option 3, when the device is in pin mode, both full-scale
values can be adjusted by sourcing or sinking current from the
REFIO pin. Noise injected here appears as amplitude modulation
of the output; therefore, a portion of the required series resis-
tance (at least 10 kΩ) must be installed at the pin. A range of
±25% is quite practical when using this method.
Fine Gain
Each main DAC has independent fine gain control using the
lower six bits in Register 0x03 (I DAC gain) and Register 0x06
(Q DAC gain). Unlike Coarse Gain Option 1, this impacts only
the main DAC full-scale output current. These registers use straight
binary format. One application in which straight binary format
is critical is for side-band suppression while using a quadrature
modulator. This is described in more detail in the Applications
Information section.
2.22
2.20
2.18
2.16
2.14
2.12
2.10
0
8
16
24
32
40
48
56
64
GAIN DAC CODE
I O
U
TFS
(m
A
)
07
26
5-
0
5
6
3.3V DAC1
3.3V DAC2
1.8V DAC1
1.8V DAC2
Figure 100. Typical DAC Gain Characteristics
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| AD9716-DPG2-EBZ | 功能描述:ADC 12BIT DUAL 40LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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| AD9717BCPZ | 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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