參數(shù)資料
型號： AD9716BCPZRL7
廠商： Analog Devices Inc
文件頁數(shù)： 40/80頁
文件大?。?/td> 0K
描述： IC DAC DUAL 12BIT LO PWR 40LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 750
系列： TxDAC®
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 86mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 125M
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 45 of 80
SELF-CALIBRATION
The AD9714/AD9715/AD9716/AD9717 have a self-calibration
feature that improves the DNL of the device. Performing a self-
calibration on the device improves device performance in low
frequency applications. The device performance in applications
where the analog output frequencies are above 5 MHz are generally
influenced more by dynamic device behavior than by DNL and,
in these cases, self-calibration is unlikely to provide much benefit.
The calibration clock frequency is equal to the DAC clock
divided by the division factor chosen by the DIVSEL value. Each
calibration clock cycle is between 32 and 2048 DAC input clock
cycles, depending on the value of DIVSEL[2:0] (Register 0x0E,
Bits[2:0]). The frequency of the calibration clock should be
between 0.5 MHz and 4 MHz for reliable calibrations. Best
results are obtained by setting DIVSEL[2:0] (Register 0x0E,
Bits[2:0]) to produce a calibration clock frequency between
these values. Separate self-calibration hardware is included
for each DAC. The DACs can be self-calibrated individually or
simultaneously.
To perform a device self-calibration, the following procedure
can be used:
1.
Write 0x00 to Register 0x12. This ensures that the
UNCALI and UNCALQ bits are reset.
2.
Set up a calibration clock between 0.5 MHz and 4 MHz
using DIVSEL[2:0], and then enable the calibration clock
by setting the CALCLK bit (Register 0x0E, Bit 3).
3.
Select the DAC(s) to self-calibrate by setting either Bit 4
(CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E. Note that each DAC contains
independent calibration hardware so that they can be
calibrated simultaneously.
4.
Start self-calibration by setting the CALEN bit (Register 0x12,
Bit 4). Wait approximately 300 calibration clock cycles.
5.
Check if the self-calibration has completed by reading
the CALSTATI bit (Bit 6) and CALSTATQ bit (Bit 7) in
Register 0x0F. Logic 1 indicates that the calibration has
completed.
6.
When the self-calibration has completed, write 0x00 to
Register 0x12.
7.
Disable the calibration clock by clearing the CALCLK bit
(Register 0x0E, Bit 3).
The AD9714/AD9715/AD9716/AD9717 allow reading and
writing of the calibration coefficients. There are 32 coefficients
in total. The read/write feature of the coefficients can be useful
for improving the results of the self-calibration routine by
averaging the results of several self-calibration cycles and
loading the averaged results back into the device.
To read the calibration coefficients, use the following steps:
1.
Select which DAC core to read by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E. Write the address of the first
coefficient (0x01) to Register 0x10.
2.
Set the SMEMRD bit (Register 0x12, Bit 2) by writing 0x04
to Register 0x12.
3.
Read the 6-bit value of the first coefficient by reading the
contents of Register 0x11.
4.
Clear the SMEMRD bit by writing 0x00 to Register 0x12.
5.
Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by 1 for each read.
6.
Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
To write the calibration coefficients to the device, use the
following steps:
1.
Select which DAC core to write to by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q
DAC in Register 0x0E.
2.
Set the SMEMWR bit (Register 0x12, Bit 3) by writing 0x08
to Register 0x12.
3.
Write the address of the first coefficient (0x01) to
Register 0x10.
4.
Write the value of the first coefficient to Register 0x11.
5.
Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by one for each
write.
6.
Clear the SMEMWR bit by writing 0x00 to Register 0x12.
7.
Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
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參數(shù)描述
AD9716-DPG2-EBZ 功能描述:ADC 12BIT DUAL 40LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9716-EBZ 制造商:Analog Devices 功能描述:DUAL 12 BIT LOW POWER CONVERTER - Boxed Product (Development Kits) 制造商:Rochester Electronics LLC 功能描述:
AD9717 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters
AD9717BCPZ 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF)
AD9717BCPZ 制造商:Analog Devices 功能描述:IC DAC 14BIT 125MSPS LFCSP-40
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