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參數(shù)資料
| 型號(hào)： | AD9735BBCZRL |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 33/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 1.2GSPS 160-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 550mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 160-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 160-CSPBGA（12x12） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 2 電流，單極 |
| 采樣率（每秒）： | 1.2G |
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AD9734/AD9735/AD9736
Rev. A | Page 39 of 72
INTERPOLATION FILTER
In 2× mode, the input data is interpolated by a factor of 2 so
that it aligns with the DAC update rate. The interpolation filter
is a hard-coded, 55-tap, symmetric FIR with a 0.001 dB pass-
band flatness and a stop-band attenuation of about 90 dB. The
transition band runs from 20% of fDAC to 30% of fDAC. The FIR
response is shown in Figure 75 where the frequency axis is
Table 23 shows the 16-bit filter coefficients.
Table 23. FIR Interpolation Filter Coefficients
Coefficient Number
Tap Weight
1
55
7
2
54
0
3
53
+24
4
52
0
5
51
62
6
50
0
7
49
+135
8
48
0
9
47
263
10
46
0
11
45
+471
12
44
0
13
43
793
14
42
0
15
41
+1273
16
40
0
17
39
1976
18
38
0
19
37
+3012
20
36
0
21
35
4603
22
34
0
23
33
+7321
24
32
0
25
31
13270
26
30
0
27
29
+41505
28
+65535
04862-073
FREQUENCY NORMALIZED TO
fDAC
0.50
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
MAGNIT
UDE
(d
B)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Figure 75. Interpolation Filter Response
04862-074
FREQUENCY NORMALIZED TO
fDAC
0.25
0
0.10
0.05
0.15
0.20
MA
GN
ITU
D
E
(
d
B
)
0.10
0.06
0.08
0.02
–0.02
–0.06
0.04
0
–0.04
–0.08
–0.10
Figure 76. Interpolation Filter Pass-Band Flatness
DATA INTERFACE CONTROLLERS
Two internal controllers are utilized in the operation of the
AD973x. The first controller helps maintain optimum LVDS
data sampling; the second controller helps maintain optimum
synchronization between the DACCLK and the incoming data.
The LVDS controller is responsible for optimizing the sampling
of the data from the LVDS bus (DB13:0), while the sync
controller resolves timing problems between the DAC_CLK
(CLK+, CLK) and the DATACLK. A block diagram of these
controllers is shown in Figure 77.
DATACLK_OUT
DATACLK
DATACLK_IN
FIFO
DAC
LVDS
SAMPLE
LOGIC
CLK
CONTROL
LVDS
CONTROLLER
DB<13:0>
DATA
SOURCE
i.e., FPGA
SYNC
LOGIC
SYNC
CONTROLLER
04862-075
Figure 77. Data Controllers
The controllers are clocked with a divided-down version of the
DAC_CLK. The divide ratio is set utilizing the controller clock
predivider bits (CCD<3:0>) located at Reg. 22, Bits 3:0 to
generate the controller clock as follows:
Controller Clock = DAC_CLK/(2(CCD<3:0> + 4))
Note that the controller clock cannot exceed 10 MHz for correct
operation. Until CCD<3:0> is properly programmed to meet
this requirement, the DAC output may not be stable. This
means the FIFO cannot be enabled in PIN_MODE unless the
DACCLK is less than 160 MHz.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9735BBCZRL1 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS |
| AD9735-DPG2-EBZ | 功能描述:BOARD EVAL FOR AD9735 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9735-EB | 制造商:Analog Devices 功能描述: |
| AD9735-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9735 DAC, 10-/12-/14-Bit, 1200 MSPS DACs 制造商:Analog Devices 功能描述:EVAL BD FOR AD9735 DAC, 10-/12-/14BIT, 1200 MSPS DACS - Bulk |
| AD9736 | 制造商:Analog Devices 功能描述:14-BIT, 1.2 GSPS TXDAC+? D/A CONVERTER - Bulk |
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