參數(shù)資料
型號(hào): AD9735BBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 7/72頁
文件大?。?/td> 0K
描述: IC DAC 12BIT 1.2GSPS 160-CSPBGA
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 550mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 160-CSPBGA(12x12)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 1.2G
AD9734/AD9735/AD9736
Rev. A | Page 15 of 72
Pin No.
Mnemonic
Description
K13, K14
DB<9>/DB<9>+
Negative/Positive Data Input Bit 9 (MSB). Conforms to IEEE-1596
reduced range link.
L1
PIN_MODE
0 = SPI Mode. SPI is enabled.
1 = PIN Mode. SPI is disabled; direct pin control.
L7, L8, M7, M8, N7, N8, P7, P8
DVDD33
3.3 V Digital Supply.
L13, L14
DB<8>/DB<8>+
Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced
range link.
M1, M2
NC
No Connect.
M13, M14
DB<7>/DB<7>+
Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced
range link.
N1, P1
NC
No Connect.
N2, P2
NC
No Connect.
N3, P3
NC
No Connect.
N4, P4
DB<0>/DB<0>+
Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596
reduced range link.
N5, P5
DB<1>/DB<1>+
Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced
range link.
N6, P6
DATACLK_OUT/
DATACLK_OUT+
Negative/Positive Data Output Clock. Conforms to IEEE-1596
reduced range link.
N9, P9
DATACLK_IN/
DATACLK_IN+
Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced
range link.
N10, P10
DB<2>/DB<2>+
Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced
range link.
N11, P11
DB<3>/DB<3>+
Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced
range link.
N12, P12
DB<4>/DB<4>+
Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced
range link.
N13, P13
DB<5>/DB<5>+
Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced
range link.
N14, P14
DB<6>/DB<6>+
Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced
range link.
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