參數(shù)資料
型號(hào)： AD9735BBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 37/72頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT 1.2GSPS 160-CSPBGA
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 550mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 160-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 160-CSPBGA（12x12）
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 2 電流，單極
采樣率（每秒）： 1.2G
AD9734/AD9735/AD9736
Rev. A | Page 42 of 72
SYNC LOGIC AND CONTROLLER
A FIFO structure is utilized to synchronize the data transfer
between the DACCLK and the DATACLK_IN clock domains.
The sync controller writes data from DB<13:0> into an 8-word
memory register based on a cyclic write counter clocked by the
DSS, which is a delayed version of DACCLK_IN. The data is
read out of the memory based on a second cyclic read counter
clocked by DACCLK. The 8-word FIFO shown in Figure 82
provides sufficient margin to maintain proper timing under
most conditions. The sync logic is designed to prevent the read
and write pointers from crossing. If the timing drifts far enough
to require an update of the phase offset (PHOF<1:0>), two
samples are duplicated or dropped. Figure 83 shows the timing
diagram for the sync logic.
8 WORD
MEMORY
READ
COUNTER
PHOF<1:0>
DACCLK
FIFOSTAT<2:0>
DSS
M0
M7
ZD
DAC<13:0>
ADDER
WRITE
COUNTER
FF
DAC<13:0>
04862-080
Figure 82. Sync Logic Block Diagram
SYNC LOGIC AND CONTROLLER OPERATION
The relationship between the readout pointer and the write
pointer initially is unknown because the startup relationship
between DACCLK and DATACLK_IN is unknown. The sync
logic measures the relative phase between the two counters with
the zero detect block and the flip-flop in Figure 82. The relative
phase is returned in FIFOSTAT<2:0> (Reg. 7, Bits 6:4), and sync
logic errors are indicated by FIFOSTAT<3> (Reg. 7, Bit 7). If
FIFOSTAT<2:0> returns a value of 0 or 7, the memory is
sampling in a critical state (read and write pointers are close to
crossing).
If the FIFOSTAT<2:0> returns a value of 3 or 4, the memory is
sampling at the optimal state (read and write pointers are
farthest apart). If FIFOSTAT<2:0> returns a critical value, the
pointer can be adjusted with the phase offset PHOF<1:0> (Reg.
7, Bits 1:0). Due to the architecture of the FIFO, the phase offset
can only adjust the read pointer in steps of 2.
OPERATION IN MANUAL MODE
To start operating the DAC in manual mode, allow DACCLK
and DATACLK_IN to stabilize, then enable FIFO mode (Reg. 0,
Bit 2). Read FIFOSTAT<2:0> (Reg. 7, Bits 6:4) to determine if
adjustment is needed. For example, if FIFOSTAT<2:0> = 6, the
timing is not yet critical, but it is not optimal.
To return to an optimal state (FIFOSTAT<2:0> = 4), the
PHOF<1:0> (Reg. 7, Bits 1:0) needs to be set to 1. Setting
PHOF<1:0> = 1 effectively increments the read pointer by 2.
This causes the write pointer value to be captured two clocks
later, decreasing FIFOSTAT<2:0> from 6 to 4.
OPERATION IN SURVEILLANCE AND AUTO MODES
Once FIFOSTAT<2:0> is manually placed in an optimal state,
the AD973x sync logic can run in surveillance or auto mode. To
start, turn on surveillance mode by setting SSURV = 1 (Reg. 8,
Bit 7), then enable the sync interrupt (Reg. 1, Bit 2).
If STRH<0> = 0 (Reg. 8, Bit 0), an interrupt occurs if
FIFOSTAT<2:0> = 0 or 7. If STRH<0> = 1 (Reg. 8, Bit 0), an
interrupt occurs if FIFOSTAT<2:0> = 0, 1, 6, or 7. The interrupt
is read at Reg. 1, Bit 6 at the AD973x IRQ pin.
To enter auto mode, complete the preceding steps then set
SAUTO = 1 (Reg. 8, Bit 6). Next, set the sync interrupt = 0
(Reg. 1, Bit 2), to allow the phase offset (PHOF<1:0>) to be
automatically updated if FIFOSTAT<2:0> violates the threshold
value. The FIFOSTAT signal is filtered to improve noise
immunity and reduce unnecessary phase offset updates. The
filter operates with the following algorithm:
FIFOSTAT = FIFOSTAT + ΔFIFOSTAT/2 ^ SFLT<3:0>
where:
0 ≤ SFLT<3:0> ≤ 12
Values greater than 12 are set to 12. If SFLT<3:0> is too small,
clock jitter and noise can cause erratic behavior. Normally, SFLT
can be set to the maximum value.
FIFO BYPASS
When the FIFO_MODE bit (Reg. 1, Bit 2) is set to 0, the FIFO
is bypassed with a mux. When the FIFO is enabled, the pipeline
delay through the AD973x increases by the delta between the
FIFO read pointer and write pointer plus 4 more clock periods.
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參數(shù)描述
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AD9736 制造商:Analog Devices 功能描述:14-BIT, 1.2 GSPS TXDAC+? D/A CONVERTER - Bulk
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