參數(shù)資料
型號： AD9779A-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 24/56頁
文件大小： 0K
描述： BOARD EVALUATION FOR AD9779A
設計資源： Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016)
Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017)
Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018)
Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019)
Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020)
Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
AD9788-79A Eval Brd Schematic
AD9779A-DPG2-EBZ BOM
AD9779A-DPG2-EBZ Gerber Files
標準包裝： 1
系列： *
DAC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 1G
數(shù)據(jù)接口： 串行
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9779A
AD9776A/AD9778A/AD9779A
Rev. B | Page 30 of 56
Register
Address
Bits
Register Name
Parameter
Function
Default
Sync Control
0x03
7
DATACLK delay mode
0: manual data timing error detect mode.
1: automatic data timing error detect mode.
0
0x03
6
Reserved
Should always be set to 1.
0
0x03
5:4
DATACLK Divide[1:0]
DATACLK output divider value.
00: divide by 1.
01: divide by 2.
10: divide by 4.
11: divide by 1.
00
0x03
3:0
Data Timing Margin[3:0]
Sets the timing margin required to prevent the
data timing error IRQ bit from being asserted.
0000
0x04
7:4
DATACLK Delay[3:0]
Sets delay of REFCLK input to DATACLK output (see
Table 29 for details).
0000
0x04
3:1
SYNC_O Divide[2:0]
The frequency of the SYNC_O signal is equal to
fDAC/N, where N is set as follows:
000: N = 32.
001: N = 16.
010: N = 8.
011: N = 4.
100: N = 2.
101: N = 1.
110: N = undefined.
111: N = undefined.
000
0x04
0x05
0
7:4
SYNC_O Delay[4]
SYNC_O Delay[3:0]
The SYNC_O Delay[4:0] value programs the value
of the delay line of the SYNC_O signal. The delay of
SYNC_O is relative to REFCLK. The delay line
resolution is 80 ps per step.
00000: nominal delay.
00001: adds 80 ps delay to SYNC_O.
00010: adds 160 ps delay to SYNC_O.
…
11111: Adds 2480 ps delay to SYNC_O.
0
0000
0x05
3:1
SYNC_I Ratio[2:0]
This value controls the number of SYNC_I input
pulses required to generate a synchronization
pulse (see Table 30 for details).
000
0x05
0x06
0
7:4
SYNC_I Delay[4]
SYNC_I Delay[3:0]
The SYNC_I Delay[4:0] value programs the value of
the delay line of the SYNC_I signal. The delay line
resolution is 80 ps per step.
00000: nominal delay.
00001: adds 80 ps delay to SYNC_I.
00010: adds 160 ps delay to SYNC_I.
…
11111: adds 2480 ps delay to SYNC_I.
0
0000
0x06
3:0
SYNC_I Timing Margin[3:0]
0000
0x07
7
SYNC_I enable
1: enables the SYNC_I input.
0
0x07
6
SYNC_O enable
1: enables the SYNC_O output.
0
0x07
5
SYNC_O triggering edge
0: SYNC_O changes on REFCLK falling edge.
1: SYNC_O changes on REFCLK rising edge.
0
0x07
4:0
Clock State[4:0]
This value determines the state of the internal
clock generation state machine upon
synchronization.
0
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