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參數(shù)資料
| 型號： | AD9779A-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9779A |
| 設(shè)計資源： | Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021) AD9788-79A Eval Brd Schematic AD9779A-DPG2-EBZ BOM AD9779A-DPG2-EBZ Gerber Files |
| 標準包裝： | 1 |
| 系列： | * |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1G |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | * |
| 已用 IC / 零件： | AD9779A |
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AD9776A/AD9778A/AD9779A
Rev. B | Page 41 of 56
Configuring PLL Band Select with Temperature Sensing
The following procedure outlines a method for setting the PLL
band select value for a device operating at a particular temperature
that holds for a change in ambient temperature over the total
40°C to +85°C operating range of the device without further
user intervention. Note that REFCLK must be applied to the
device during this procedure.
1.
Program the values of N1 (Register 0x09, Bits[6:5]) and N2
(Register 0x09, Bits[4:3]), along with the PLL settings
shown in Table 22.
2.
Set the PLL band (Register 0x08, Bits[7:2]) to 63 to enable
PLL auto mode.
3.
Wait for the PLL_LOCK pin or the PLL lock indicator
(Register 0x00, Bit 1) to go high. This should occur
within 5 ms.
4.
Read back the 6-bit PLL band (Register 0x08, Bits[7:2]).
5.
Based on the temperature when the PLL auto band select is
performed, set the PLL band indicated in either Table 24 or
Table 25 by rewriting the readback values into the PLL
Band Select parameter (Register 0x08, Bits[7:2]).
This procedure requires temperature sensing upon start-up or
reset of the device to optimally choose the PLL band select
value that holds over the entire operating temperature range. If
the optimal band is in the range of 0 to 31 (lower VCO
frequency), refer to Table 24.
Table 24. Setting Optimal PLL Band, When Band Is in the
Lower Range (0 to 31)
If System Startup
Temperature Is
Set PLL Band as Follows
40°C to 10°C
Set PLL band = readback band + 2
10°C to +15°C
Set PLL band = readback band + 1
15°C to 55°C
Set PLL band = readback band
55°C to 85°C
Set PLL band = readback band 1
If the optimal band is in the range of 32 to 62 (higher VCO
frequency), refer to Table 25.
Table 25. Setting Optimal PLL Band, When Band Is in the
Higher Range (32 to 62)
If System Startup
Temperature Is
Set PLL Band as Follows
40°C to 30°C
Set PLL band = readback band + 3
30°C to 10°C
Set PLL band = readback band + 2
10°C to +15°C
Set PLL band = readback band + 1
15°C to 55°C
Set PLL band = readback band
55°C to 85°C
Set PLL band = readback band 1
Known Temperature Calibration with Memory
If temperature sensing is not available in the system, a factory
calibration at a known temperature is another method for
guaranteeing lock over temperature. Factory calibration can be
performed as follows:
1.
Program the values of N1 (Register 0x09, Bits[6:5]) and N2
(Register 0x09, Bits[4:3]), along with the PLL settings
shown in Table 22.
2.
Set the PLL band (Register 0x08, Bits[7:2]) to 63 to enable
PLL auto mode.
3.
Wait for the PLL_LOCK pin or the PLL lock indicator
(Register 0x00, Bit 1) to go high. This should occur
within 5 ms.
4.
Read back the 6-bit PLL band (Register 0x08, Bits[7:2]).
5.
Based on the temperature when the PLL auto band select is
performed, store into nonvolatile memory the PLL band
up or restart, load the stored PLL band value into the PLL
band select parameter (Register 0x08, Bits[7:2]).
Set-and-Forget Device Option
If the PLL band select configuration methods described in
the previous sections cannot be implemented in a particular
system, there may be a screened device option that can satisfy
the system requirements. This allows the user to preload a
specific PLL band select value for all devices that holds over
temperature. Example REFCLK and VCO frequencies are
shown in Table 26.
Table 26. Typical VCO Frequency Range vs.
PLL Band Select Value
fREFCLK (MHz)
fVCO (MHz)
Guaranteed
PLL Band
Total PLL
Divide Ratio
59.73335
955.7336
2
16
61.44
1966.08
61
32
67.2
1075.2
11
16
76.8
1228.8
20
16
80.01
1280
23
16
81.92
1310.72
25
16
92.16
1474.56
34
16
112.0
1792.0
50
16
119.4667
955.7336
2
8
122.88
1966.08
61
16
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| AD9779BSVZ | 功能描述:IC DAC 16BIT DUAL 1GSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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