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參數(shù)資料
| 型號： | AD9911/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/44頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9911 |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設計資源： | AD9911 Eval Brd Schematics AD9911 Eval Brd BOM AD9911 Eval Brd Gerber Files |
| 標準包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9911 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | AD9911BCPZ-REEL7-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP AD9911BCPZ-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP |
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AD9911
Rev. 0 | Page 20 of 44
DATA
ALIGN
10-BIT DAC
DAC 1
COS(X)
DDS CORE 1
MUX
0
CFR <18:16>
10
COS(X)
DDS CORE 0
COS(X)
DDS CORE 2
COS(X)
DDS CORE 3
10
3
10
3
05
78
5-
03
5
DATA
ALIGN
DATA
ALIGN
Figure 36. SpurKiller/Multitone Mode Configuration
TEST-TONE MODE
Test-tone mode enables sinusoidal amplitude modulation of the
carrier (CH1). Setting Bit 2 in Register 0x01 enables test-tone
mode. Auxiliary CH2 and CH3 should both be disabled using
the channel enable bits (CSR Bit <7>). The frequency of
modulation is set using the frequency tuning word
(Register 0x04 Bits <31:0>) of auxiliary CH0. Auxiliary CH0
output scalar (Register 0x06 Bits <0:9>) sets the magnitude of
the modulating signal. See Figure 37 for a diagram of the test-
tone mode configuration.
DAC 1
COS(X)
DDS CORE 1
10
14
10
COS(X)
DDS CORE 0
PHASE OFFSET
AMPLITUDE
05
78
5-
0
36
Figure 37. Test-Tone Mode Configuration
REFERENCE CLOCK MODES
The AD9911 supports several methods for generating the
internal system clock. An on-chip oscillator circuit is available
for initiating the low frequency reference signal by connecting
a crystal to the clock input pins. The system clock can also be
generated using the internal, PLL-based reference clock
multiplier, allowing the part to operate with a low frequency
clock source while still providing a high sample rate for the
DDS and DAC. For best phase noise performance, a clean,
stable clock with a high slew rate is required.
Enabling the PLL allows multiplication of the reference clock
frequency from 4× to 20×, in integer steps. The PLL multiplica-
tion value is 5-bits located in the Function Register 1 (FR1) Bits
<22:18>. For further information, refer to the Register Map
section.
When FR1 <22:18> is programmed with values ranging from 4 to
20 (decimal), the clock multiplier is enabled. The integer value in
the register represents the multiplication factor. The system clock
rate with the clock multiplier enabled is equal to the reference clock
rate times the multiplication factor. If FR1 <22:18> is programmed
with a value less than 4 or greater than 20, the clock multiplier is
disabled. Note that the output frequency of the PLL has a restricted
frequency range. There is a VCO gain bit that must be set
appropriately. The VCO gain bit (FR1<23>) defines two ranges
(low/high) of frequency output. See the Register Map section for
configuration directions and defaults.
The charge pump current in the PLL defaults to 75 μA, which
typically produces the best phase noise characteristics.
Increasing charge pump current typically degrades phase noise,
but decreases the lock time and alters the loop bandwidth. The
charge pump control bits (FR1 <17:16>) function is described
in the Register Map section.
To enable the on-chip oscillator for crystal operation, drive
CLK_MODE_SEL (Pin 24) high. The CLKMODESEL pin is
considered an analog input, operating on 1.8 V logic. With the
on-chip oscillator enabled, connection of an external crystal to
the REF_CLK and REF_CLKB inputs is made producing a low
frequency reference clock. The crystal frequency must be in the
range of 20 MHz to 30 MHz. summarizes the clock mode
options. See the Register Maps section for more details.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9912 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer w/ 14-bit DAC |
| AD9912/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 1 GSPS Direct Digital Synthesizer W/ 14-Bit DAC 制造商:Analog Devices 功能描述:EVAL KIT FOR 1 GSPS DIRECT DGTL SYNTHESIZER W/ 14BIT DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD AD9912 1GSPS DDS |
| AD9912A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9912 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9912ABCPZ | 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9912ABCPZ-REEL7 | 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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