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參數(shù)資料
型號(hào)： AD9911/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 19/44頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9911
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： AD9911 Eval Brd Schematics
AD9911 Eval Brd BOM
AD9911 Eval Brd Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
已用 IC / 零件： AD9911
已供物品： 板
相關(guān)產(chǎn)品： AD9911BCPZ-REEL7-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP
AD9911BCPZ-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP
AD9911
Rev. 0 | Page 26 of 44
FTW0
SINGLE–TONE
MODE
LINEAR SWEEP MODE
PS<1> = 1
PS<1> = 0
TIME
FTW1
A
B
fOUT
05
78
5-
04
3
Figure 45. Linear Sweep Enabled-No Dwell Bit Cleared
SWEEP AND PHASE ACCUMULATOR CLEARING
FUNCTIONS
The AD9911 provides two different clearing functions. The first
function is a continuous zeroing of the sweep logic and phase
accumulator (clear and hold). CFR <3> clears the sweep
accumulator and CFR <1> clears the phase accumulator
The second function is a clear and release or automatic zeroing
function. CFR <4> is the automatic clear sweep accumulator bit
and CFR <2> is the automatic clear phase accumulator bit.
Continuous Clear Bits
The continuous clear bits are static control signals that, when
high, hold the respective accumulator at 0. When the bit is
programmed low, the respective accumulator is released.
Clear and Release Bits
The auto clear sweep accumulator bit, when set, clears and
releases the sweep accumulator upon an I/O update or a change
in the profile input pins. The auto clear phase accumulator,
when set, clears and releases the phase accumulator upon an
I/O update or a change in the profile pins. The automatic clear-
ing function is repeated for every subsequent I/O update or
change in profile pins until the clear and release bits are cleared
via the I/O port.
OUTPUT AMPLITUDE CONTROL
The output amplitude may be controlled via one of four
methods. Output amplitude control is implemented by the use
of the 10-bit output scale factor (multiplier). See Figure 46 for
output amplitude control configurations. For further details on
the corresponding methods, see the Shift Keying Modulation
sections. The remaining methods (Manual and Automatic
RU/RD) are described in this section.
The RU/RD feature is used to control an on/off emission from
the DAC. This helps reduce the adverse spectral impact of
abrupt burst transmissions of digital data. The multiplier can be
bypassed by clearing the multiplier enable bit (ACR <12> = 0).
Automatic and manual RU/RD modes are supported. The
automatic mode generates a zero to full-scale (10-bits) linear
ramp at a rate set using the amplitude ramp rate control register
(ACR <23:16>). Ramp initiation and direction (up/down) is
controlled using either the profile pins or the SDIO1:3 pins.
See Table 21. Manual mode is selected by programming ACR
<12:11> = 10. In this mode, the user sets the output amplitude
by writing to the amplitude scale factor value in the amplitude
control register (Register 0x06 Bits <9:0>).
Automatic RU/RD Mode Operation
The automatic RU/RD mode is entered by setting ACR <12:11>
= 11. In this mode, the scale factor is internally generated and
applied to the multiplier input port for scaling the output. The
scale factor is the output of a 10-bit counter that increments/
decrements at a rate set by the 8-bit output ramp rate in Register
0x06 Bits <23:16>. The scale factor increments if the external
pin is high and decrements if the pin is low. The scale factor
step size is selected using the ACR<15:14>. Table 20 details the
step size options available.
Table 20.
Autoscale Factor Step Size
ASF <15:14> (Binary)
Increment/Decrement Size
00
1
01
2
10
4
11
8
The amplitude scale factor register allows the device to ramp to
a value less than full scale.
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AD9912ABCPZ 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9912ABCPZ-REEL7 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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