參數(shù)資料
型號： AD9911/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 42/44頁
文件大小： 0K
描述： BOARD EVAL FOR AD9911
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源： AD9911 Eval Brd Schematics
AD9911 Eval Brd BOM
AD9911 Eval Brd Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
主要目的： 計時，直接數(shù)字合成（DDS）
已用 IC / 零件： AD9911
已供物品： 板
相關(guān)產(chǎn)品： AD9911BCPZ-REEL7-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP
AD9911BCPZ-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP
AD9911
Rev. 0 | Page 7 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
I/O PORT TIMING CHARACTERISTICS
Maximum Frequency Clock (SCLK)
200
MHz
Minimum SCLK Pulse Width Low (tPWL)
1.6
ns
Minimum SCLK Pulse Width High (tPWH)
2.2
ns
Minimum Data Set-Up Time (tDS)
2.2
ns
Minimum Data Hold Time
0
ns
Minimum CSB Set-Up Time (tPRE)
1.0
ns
Minimum Data Valid Time for Read Operation
12
ns
MISCELLANEOUS TIMING CHARACTERISTICS
Master_Reset Minimum Pulse Width
1
Minimum pulse width = 1 sync clock period
I/O_Update Minimum Pulse Width
1
Minimum pulse width = 1 sync clock period
Minimum Set-Up Time (I/O_Update to
SYNC_CLK)
4.8
ns
Rising edge to rising edge
Minimum Hold Time (I/O_Update to
SYNC_CLK)
0
ns
Rising edge to rising edge
Minimum Set-Up Time (Profile Inputs to
SYNC_CLK)
5.4
ns
Minimum Hold Time (Profile Inputs to
SYNC_CLK)
0
ns
Minimum Set-Up Time (SDIO Inputs to
SYNC_CLK)
2.5
ns
Minimum Hold Time (SDIO Inputs to
SYNC_CLK)
0
ns
Propagation Delay Between REF_CLK and
SYNC_CLK
2.25
3.5
5.5
ns
CMOS LOGIC INPUT
VIH
2.0
V
VIL
0.8
V
Logic 1 Current
3
12
μA
Logic 0 Current
12
μA
Input Capacitance
2
pF
CMOS LOGIC OUTPUTS (1 mA Load)
VOH
2.7
V
VOL
0.4
V
POWER SUPPLY
Total Power Dissipation—Single-Tone Mode
241
mW
Dominated by supply variation
Total Power Dissipation—With Sweep
Accumulator
241
mW
Dominated by supply variation
Total Power Dissipation—3 Spur
Reduction/Multitone Channels Active
351
mW
Dominated by supply variation
Total Power Dissipation—Test-Tone
Modulation
264
mW
Dominated by supply variation
Total Power Dissipation—Full Power Down
1.8
mW
IAVDD—Single-Tone Mode
73
mA
IAVDD— Sweep Accumulator, REF_CLK
Multiplier, and 10-Bit Output Scalar Enabled
73
mA
IDVDD—Single-Tone Mode
50
mA
IDVDD—Sweep Accumulator, REF_CLK
Multiplier, and 10-Bit Output Scalar Enabled
50
mA
IDVDD_I/O
40
mA
IDVDD = read
IDVDD_I/O
30
mA
IDVDD = write
IAVDD Power-Down Mode
0.7
mA
IDVDD Power-Down Mode
1.1
mA
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參數(shù)描述
AD9912 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer w/ 14-bit DAC
AD9912/PCBZ 制造商:Analog Devices 功能描述:Evaluation Kit For 1 GSPS Direct Digital Synthesizer W/ 14-Bit DAC 制造商:Analog Devices 功能描述:EVAL KIT FOR 1 GSPS DIRECT DGTL SYNTHESIZER W/ 14BIT DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD AD9912 1GSPS DDS
AD9912A/PCBZ 功能描述:BOARD EVALUATION FOR AD9912 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板
AD9912ABCPZ 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9912ABCPZ-REEL7 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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