參數(shù)資料
型號(hào)： AD9911/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/44頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9911
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： AD9911 Eval Brd Schematics
AD9911 Eval Brd BOM
AD9911 Eval Brd Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
已用 IC / 零件： AD9911
已供物品： 板
相關(guān)產(chǎn)品： AD9911BCPZ-REEL7-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP
AD9911BCPZ-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP
AD9911
Rev. 0 | Page 28 of 44
SYNCHRONIZING MULTIPLE AD9911 DEVICES
The AD9911 allows easy synchronization of multiple AD9911
devices. At power-up, the phase of SYNC_CLK may be offset
between multiple devices. There are three options (one
automatic mode and two manual modes) to compensate for this
offset and align the SYNC_CLK edges. These modes force the
internal state machines of multiple devices to a common state,
which aligns SYNC_CLKs.
Any mismatch in REF_CLK phase between devices results in a
corresponding phase mismatch on the SYNC_CLKs.
OPERATION
The first step is to program the master and slave devices for
their respective roles. Configure the master device by setting its
master enable bit (FR2 <6>). This causes the SYNC_OUT of the
master device to output a pulse whose pulse width equals one
system clock period and whose frequency equals of the
system clock frequency. Configuring device(s) as slaves is
performed by setting the slave enable bit (FR2 <7>).
AUTOMATIC MODE SYNCHRONIZATION
In automatic mode, synchronization is achieved by connecting
the SYNC_OUT pin on the master device to the SYNC_IN pin
of the slave device(s). Devices are configured as master or slave
through programming bits, accessible via the I/O port.
A configuration for synchronizing multiple AD9911 devices in
automatic mode is shown in the Application Circuits section. In
this configuration, the AD9510 provides coincident REF_CLK
and SYNC_IN to all devices.
In this mode, slave devices sample SYNC_OUT pulses from the
master device and a comparison of all state machines is made
by the auto-synchronization circuitry. If the slave device(s) state
machines are not identical to the master, the slave device(s)
state machines stall for one system clock cycle. This procedure
synchronizes the slave device(s) within three SYNC_CLK
periods.
Delay Time Between SYNC_OUT and SYNC_IN
When the delay between SYNC_OUT and SYNC_IN exceeds
one system clock period, phase offset bits (FR2 <1:0>) are used
to compensate. Without the compensation factor, a phase error
of 90°, 180°, or 270° might exist. The default state of these bits is
00, which implies that the SYNC_OUT of the master and the
SYNC_IN of the slave have a propagation delay of less than one
system clock period.
If the propagation time is greater than one system clock period,
the time should be measured and the appropriate offset
programmed. Table 21 describes the delays required per system
clock offset value.
Table 21.
System Clock
Offset Value
SYNC_OUT/SYNC_IN
Propagation Delay
00
0 ≤ delay ≤ 1
01
1 ≤ delay ≤ 2
10
2 ≤ delay ≤ 3
11
3 ≤ delay ≤ 4
Automatic Synchronization Status Bit
If a slave device falls out of sync, the sync status bit is set. This
bit can be read through the I/O port bit (FR2 <5>). It clears
automatically when read. If the device reacquires sync before
the bit is read, the alarm will remain high. The bit does not
necessarily reflect the current state of the device. The status bit
can be masked by writing Logic 1 to the synchronization status
mask bit (FR2 <4>). When masked, the bit is held low.
MANUAL SOFTWARE MODE SYNCHRONIZATION
The manual software mode is enabled by setting the manual
synchronization bit (FR1 <0>). In this mode, the I/O update
that resets the Manual SW synchronization bit stalls the state
machine of the clock generator for one system clock cycle.
Stalling the clock generation state machine by one cycle changes
the phase relationship of SYNC_CLK between devices by one
system clock period (90°).
Note that the user may repeat this process until the devices have
the corresponding SYNC_CLK signals in the desired phase
relationship. The SYNC_IN input can be left floating since this
input has an internal pull-up. The SYNC_OUT is not used.
MANUAL HARDWARE MODE SYNCHRONIZATION
Manual hardware mode is enabled by setting the manual SW
synchronization bit (FR1 <1>). In this mode, the SYNC_CLK
stalls by one system clock cycle each time a rising edge is
detected on the SYNC_IN input. Stalling the SYNC_CLK state
machine by one cycle changes the phase relationship of
SYNC_CLK between devices by one system clock period (90°).
Note that the process can be repeated until the devices have
SYNC_CLK signals in the desired phase relationship. The
SYNC_IN input can be left floating since this input has an
internal pull-up. The SYNC_OUT is not used.
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參數(shù)描述
AD9912 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer w/ 14-bit DAC
AD9912/PCBZ 制造商:Analog Devices 功能描述:Evaluation Kit For 1 GSPS Direct Digital Synthesizer W/ 14-Bit DAC 制造商:Analog Devices 功能描述:EVAL KIT FOR 1 GSPS DIRECT DGTL SYNTHESIZER W/ 14BIT DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD AD9912 1GSPS DDS
AD9912A/PCBZ 功能描述:BOARD EVALUATION FOR AD9912 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板
AD9912ABCPZ 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9912ABCPZ-REEL7 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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