參數(shù)資料
型號(hào)： ADATE207BBPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/36頁(yè)
文件大小： 0K
描述： IC TIMING FORMATTER QUAD 256BGA
標(biāo)準(zhǔn)包裝： 1
類型： 四針定時(shí)格式器
PLL： 是
主要目的： 自動(dòng)測(cè)試設(shè)備
電路數(shù)： 4
頻率 - 最大： 100MHz
電源電壓： 2.375 V ~ 2.625 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 256-BGA（27x27）
包裝： 托盤
ADATE207
Rev. 0 | Page 6 of 36
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
VDD
0.3 V to +2.8 V
Digital Inputs
0.3 V to VDD + 0.3 V
Resistor Termination pins
0.3 to VDD + 0.3 V
Resistor Termination Current
12 mA max
Termination Pad Current
12 mA max
Junction Temperature
125°C
Storage Temperature
40 to 125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. Recommended Operating/Environmental
Conditions
Parameter
Min
Typ
Max
Unit
VDD
2.375
2.5
2.625
V
Case Temperature (TC)
85
°C
Relative Humidity
(Noncondensing)
85
%
THERMAL RESISTANCE
Table 5. Thermal Resistance
Package Type
θJA
θJC
Unit
256-Lead BGA_ED
1.5
°C/W
In Still Air
14.3
°C/W
200 LFPM
12.0
°C/W
400 LFPM
11.2
°C/W
BYPASSING SCHEME
For decoupling, best practice suggests that to preserve as much
of the plane-to-plane capacitance as possible, do not perforate
the planes for VSS and VDD. Secondly, it is advisable to decouple
VDD to VSS by using 0.1 μF high frequency ceramic capacitors.
The trace to the capacitor should be kept to an absolute minimum
length. It is recommend that one capacitor be placed in the
corner of the chip and one in the middle of each side for a total
of eight capacitors for VDD to VSS. Furthermore, decouple
IOVDD to IOVSS on each side of the device. It is recommended
that 10 μF tantalum or ceramic capacitors be used for low
frequency decoupling around the device. It is not important for
these capacitors to be close to the device.
Table 6. Data Table for 256-Lead Ball Grid Array, Thermally
Enhanced, 27 mm × 27 mm Body
Dimension
Minimum
(mm)
Nominal
(mm)
Maximum
(mm)
A
1.70
A1
0.50
0.60
0.70
A2
0.60
0.80
1.00
D
26.90
27.00
27.10
D1
24.03
24.13
24.23
E
26.90
27.00
27.10
E1
24.03
24.13
24.23
b
0.60
0.75
0.90
e
1.27
aaa
0.20
bbb
0.25
ccc
0.35
ddd
0.20
eee
0.30
fff
0.15
S
0.635
ESD CAUTION
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