Input/Output1 Type Description D5 PAT_DATA_VALID I LVCM" />
參數(shù)資料
型號： ADATE207BBPZ
廠商： Analog Devices Inc
文件頁數(shù)： 35/36頁
文件大小： 0K
描述： IC TIMING FORMATTER QUAD 256BGA
標(biāo)準(zhǔn)包裝： 1
類型： 四針定時格式器
PLL： 是
主要目的： 自動測試設(shè)備
電路數(shù)： 4
頻率 - 最大： 100MHz
電源電壓： 2.375 V ~ 2.625 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 256-BGA（27x27）
包裝： 托盤
ADATE207
Rev. 0 | Page 8 of 36
Pin No.
Mnemonic
Input/Output1
Type
Description
D5
PAT_DATA_VALID
I
LVCMOS25
Indicates Pattern Bursting. When not
asserted, edges are disabled and the drive
and expect signals are static. Clocked by
MCLK.
F3
PER_EARLY_T0EN
I
LVCMOS25
Indicates the Start of a T0 Period. Clocked
by MCLK.
E1
PER_EARLY_C0EN
I
LVCMOS25
Indicates the Start of a C0 Period. Clocked
by MCLK.
C4, D3, E4, D2, D1, E3, F4, E2
INPUT_DELAY[7:0]
I
LVCMOS25
Global Delay Input For All Edges. Clocked
by MCLK.
F18
TMU_ARM_P
D, O
Differential
open-drain
Differential Tristate Output. Noninverted TMU
ARM multiplexer output. High-Z when not
enabled.
E20
TMU_ARM_N
D, O
Differential
open-drain
Differential Tristate Output. Inverted TMU
ARM multiplexer output. High-Z when not
enabled.
E19
TMU_START_P
D, O
Differential
open-drain
Differential Tristate Output. Noninverted TMU
START multiplexer output. High-Z when not
enabled.
F17
TMU_START_N
D, O
Differential
open-drain
Differential Tristate Output. Inverted TMU
START multiplexer output. High-Z when not
enabled.
E18
TMU_STOP_P
D, O
Differential
open-drain
Noninverted TMU STOP Multiplexer Output.
Differential tristate output. High-Z when not
enabled.
D20
TMU_STOP_N
D, O
Differential
open-drain
Inverted TMU STOP Multiplexer Output.
Differential tristate output. High-Z when not
enabled.
P2
DR_DATA_CH0_P
D, O
Differential
open-drain
Noninverted DCL Drive Data Signal for
Channel 0.
P1
DR_DATA_CH0_N
D, O
Differential
open-drain
Inverted DCL Drive Data Signal for Channel 0.
G3
DR_DATA_CH1_P
D, O
Differential
open-drain
Noninverted DCL Drive Data Signal for
Channel 1.
H4
DR_DATA_CH1_N
D, O
Differential
open-drain
Inverted DCL Drive Data Signal for Channel 1.
P19
DR_DATA_CH2_P
D, O
Differential
open-drain
Noninverted DCL Drive Data Signal for
Channel 2.
P20
DR_DATA_CH2_N
DO
Differential
open-drain
Inverted DCL Drive Data Signal for Channel 2.
G18
DR_DATA_CH3_P
D, O
Differential
open-drain
Noninverted DCL Drive Data Signal for
Channel 3.
H17
DR_DATA_CH3_N
D, O
Differential
open-drain
Inverted DCL Drive Data Signal for Channel 3.
N3
DR_EN_CH0_P
D, O
Differential
open-drain
Noninverted DCL Drive Enable Signal for
Channel 0.
N2
DR_EN_CH0_N
D, O
Differential
open-drain
Inverted DCL Drive Enable Signal for Channel 0.
G2
DR_EN_CH1_P
D, O
Differential
open-drain
Noninverted DCL Drive Enable Signal for
Channel 1.
G1
DR_EN_CH1_N
D, O
Differential
open-drain
Inverted DCL Drive Enable Signal for Channel 1.
N18
DR_EN_CH2_P
D, O
Differential
open-drain
Noninverted DCL Drive Enable Signal for
Channel 2.
N19
DR_EN_CH2_N
D, O
Differential
open-drain
Inverted DCL Drive Enable Signal for Channel 2.
G19
DR_EN_CH3_P
D, O
Differential
open-drain
Noninverted DCL Drive Enable Signal for
Channel 3.
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