- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > ADATE207BBPZ (Analog Devices Inc)IC TIMING FORMATTER QUAD 256BGA PDF資料下載
參數(shù)資料
| 型號： | ADATE207BBPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/36頁 |
| 文件大小： | 0K |
| 描述： | IC TIMING FORMATTER QUAD 256BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 四針定時格式器 |
| PLL： | 是 |
| 主要目的： | 自動測試設(shè)備 |
| 電路數(shù)： | 4 |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
ADATE207
Rev. 0 | Page 16 of 36
After the power and MCLK inputs are stable, the device must be
reset using the hard reset and error reset bits. The soft reset can
be used to initialize registers at any time and does not reset the
PLL or FIFOs.
There are six rules of reset.
Rule 1—on power up, keep the hard reset pin (RESET_B)
asserted.
Rule 2—if MCLK is unstable, keep the hard reset pin
(RESET_B) asserted.
Rule 3—after MCLK is stable, keep the hard reset pin
(RESET_B) asserted for at least 20 μs.
Rule 4—after the 20 μs of Rule 3 has elapsed, assert the error
reset bit (Bit 03 in Register 0x19).
Rule 5—the hard reset signal (RESET_B) can be asserted
asynchronously to MCLK, but upon deassertion, must make
setup and hold requirements upon the MCLK.
Rule 6—the minimum pulse width of RESET_B must be at least
three MCLK periods.
Table 11. Comparison Between Normal Mode and Clock Generation Mode
Normal Mode (CLKGEN_MD_EN=0)
Clock Generator Mode(CLKGEN_MD_EN=1)
Period Start
A single signal for all four channels, I_PER_EARLY_T0EN.
Four signals, one per channel; PAT_MASK[N] operates
as a period start signal for channel N.
Waveform
Memory Selection
Each channel N is selected via the I_PAT_PATDATA_N vector
every rising edge of I_MCLK.
Waveform memory location is fixed at Address 0.
Input Delay
A single vector adjust input delay for all channels,
INPUT_DELAY.
Four vectors are available, one per channel. For each
Channel N, PAT_PATDATA_N operates as
INPUT_DELAY for Channel N.
Fail Masking
Edge N for all channels can mask the fail operation every
rising edge of I_MCLK via PAT_MASK[N].
No masking of fail operations is available.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADC0804LCN | IC ADC 8-BIT 10KSPS 1LSB 20-DIP |
| ADC0820CCM+ | IC ADC 8-BIT HS 20-SOIC |
| ADF4001BRU | IC CLOCK GEN PLL 16-TSSOP |
| ADF4002BRUZ-RL7 | IC PLL FREQUENCY SYNTH 16-TSSOP |
| ADF4007BCPZ-RL7 | IC DIVIDER/PLL SYNTHESZR 20LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADATE209 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4.0 Gbps Dual Driver |
| ADATE209BBCZ | 制造商:Analog Devices 功能描述:4.0 GBPS DUAL DRIVER - Rail/Tube |
| ADATE209BCPZ | 制造商:Analog Devices 功能描述: |
| ADATE302-02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MHz Dual Integrated DCL with Differential Drive/Receive, Level Setting DACs, and Per Pin PMU |
| ADATE302-02BBCZ | 功能描述:IC DCL ATE 500MHZ DUAL 84CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。