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參數(shù)資料
| 型號： | ADATE207BBPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING FORMATTER QUAD 256BGA |
| 標準包裝： | 1 |
| 類型： | 四針定時格式器 |
| PLL： | 是 |
| 主要目的： | 自動測試設備 |
| 電路數(shù)： | 4 |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA 裸露焊盤 |
| 供應商設備封裝： | 256-BGA（27x27） |
| 包裝： | 托盤 |
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ADATE207
Rev. 0 | Page 9 of 36
Pin No.
Mnemonic
Input/Output1
Type
Description
G20
DR_EN_CH3_N
D, O
Differential
open-drain
Inverted DCL Drive Enable Signal for Channel 3.
L20
LJ_CLK_P
D, I
Differential
input
Noninverted Low Jitter Clock Input. This pin
can be multiplexed onto DR_DATA outputs
for Channel 2 and Channel 3.
K19
LJ_CLK_N
D, I
Differential
Input
Inverted Low Jitter Clock Input. This pin can
be multiplexed onto DR_DATA outputs for
Channel 2 and Channel 3.
M3
COMP_H_CH0_P
D, I
Differential
input
terminated
Noninverted DCL High Comparator Signal for
Channel 0. Differential signal is Logic 1 when
the DUT output is higher than VOH.
M2
COMP_H_CH0_N
D, I
Differential
input
terminated
Inverted DCL High Comparator Signal for
Channel 0.
J4
COMP_H_CH1_P
D, I
Differential
input
terminated
Noninverted DCL High Comparator Signal for
Channel 1. Differential signal is Logic 1 when
the DUT output is higher than VOH.
J3
COMP_H_CH1_N
D, I
Differential
input
terminated
Inverted DCL High Comparator Signal for
Channel 1.
M18
COMP_H_CH2_P
D, I
Differential
input
terminated
Noninverted DCL High Comparator Signal for
Channel 2. Differential signal is Logic 1 when
the DUT output is higher than VOH.
M19
COMP_H_CH2_N
D, I
Differential
input
terminated
Inverted DCL High Comparator Signal for
Channel 2.
J17
COMP_H_CH3_P
D, I
Differential
input
terminated
Noninverted DCL High Comparator Signal for
Channel 3. Differential signal is Logic 1 when
the DUT output is higher than VOH.
J18
COMP_H_CH3_N
D, I
Differential
input
terminated
Inverted DCL High Comparator Signal for
Channel 3.
L3
COMP_L_CH0_P
D, I
Differential
input
terminated
Noninverted DCL Low Comparator Signal for
Channel 0. Differential signal is Logic 1 when
the DUT output is higher than VOL.
L4
COMP_L_CH0_N
D, I
Differential
input
terminated
Inverted Low Comparator Signal for Channel 0.
H1
COMP_L_CH1_P
D, I
Differential
input
terminated
Noninverted DCL Low Comparator Signal for
Channel 1. Differential signal is Logic 1 when
the DUT output is higher than VOL.
J2
COMP_L_CH1_N
D, I
Differential
input
terminated
Inverted Low Comparator Signal for Channel 1.
L18
COMP_L_CH2_P
D, I
Differential
input
terminated
Noninverted DCL Low Comparator Signal for
Channel 2. Differential signal is Logic 1 when
the DUT output is higher than VOL.
L17
COMP_L_CH2_N
D, I
Differential
Input
terminated
Inverted Low Comparator Signal for Channel 2.
H20
COMP_L_CH3_P
D, I
Differential
input
terminated
Noninverted DCL Low Comparator Signal for
Channel 3. Differential signal is Logic 1 when
the DUT output is higher than VOL.
J19
COMP_L_CH3_N
D, I
Differential
input
terminated
Inverted Low Comparator Signal for Channel 3.
M1
COMP_L_CH0_T
A, I, O
Analog
Center Tap. Center tap of two 50 Ω resistor
terminations for the low comparator
differential inputs of Channel 0.
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