tCH <" />
參數(shù)資料
型號: ADATE302-02BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 33/58頁
文件大?。?/td> 0K
描述: IC DCL ATE 500MHZ DUAL 100TQFP
標準包裝: 1
類型: DCL
應用: 自動測試設備
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
ADATE302-02
Rev. A | Page 39 of 58
SERIAL PERIPHERAL INTERFACE DETAILS
07
27
8-
0
03
SCLK
CS
SDIN
tCH
tCL
tCSSA
tCSHA
tCSHD
tCSSD
tDH
tDS
tCSW
SDOUT
DO_2LAST
DO_12LAST
DO_13LAST
DO_14LAST
DO_15LAST
DO_1LAST
DO_0LAST
tDO
DATA[14]
DATA[15]
CH[1]
R/W
ADDR[1]
ADDR[0]
Figure 76. SPI Timing Diagram
Table 18. Serial Peripheral Interface Timing Requirements
Symbol
Parameter
Min
Max
Unit
tCH
SCLK minimum high
9.0
ns
tCL
SCLK minimum low
9.0
ns
tCSHA
CS assert hold
3.0
ns
tCSSA
CS assert setup
3.0
ns
tCSHD
CS deassert hold
3.0
ns
tCSSD
CS deassert setup
3.0
ns
tDH
SDIN hold
3.0
ns
tDS
SDIN setup
3.0
ns
tDO
SDOUT Data Out
15.0
ns
tCSW
CS minimum between assertions1
2
SCLK cycles
CS minimum directly after a read request
3
SCLK cycles
tCSTP
Minimum delay after CS is deasserted before SCLK can be
stopped (not shown in
); this allows any internal
operations to complete
16
SCLK cycles
1 Extra cycle is needed after read request to prime read data into SPI shift register.
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