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參數(shù)資料
| 型號(hào)： | ADC12451883 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| 中文描述： | 動(dòng)態(tài)息審查自校準(zhǔn)12位帶符號(hào)的A / D轉(zhuǎn)換器的采樣保持電路 |
| 文件頁(yè)數(shù)： | 14/18頁(yè) |
| 文件大?。?/td> | 311K |
| 代理商： | ADC12451883 |
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3.0 Analog Considerations
(Continued)
TL/H/11025–20
FIGURE 4a. Low Drift Extremely Stable Reference Circuit
TL/H/11025–21
Errors without any trims:
25
§
C
b
40
§
C to
a
85
§
C
g
0.2%
g
0.024%
g
(/2
LSB
Full Scale
Zero
Linearity
FIGURE 4b. Simple Reference Circuit
g
0.075%
g
0.024%
g
(/2
LSB
In a ratiometric system, the analog input voltage is propor-
tional to the voltage used for the A/D reference. When this
voltage is the system power supply, the V
REF
pin can be
tied to V
CC
. This technique relaxes the stability requirement
of the system reference as the analog input and A/D refer-
ence move together maintaining the same output code for a
given input condition.
For absolute accuracy, where the analog input varies be-
tween very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will re-
quire an initial adjustment to null out full-scale errors.
3.2 ACQUISITION WINDOW
As shown in the timing diagrams there are three different
methods of starting a conversion, each of which affects the
acquisition window and timing.
With Auto-Zero high a conversion can be started with the
WR or S/H controls. In either method of starting a conver-
sion the rising edge of EOC signals the actual beginning of
the acquisition window. At this time a voltage spike may be
noticed on the analog input of the ADC12451 whose ampli-
tude is dependent on the input voltage and the source re-
sistance. The timing diagrams for these two methods of
starting a conversion do not show the acquisition window
starting at this time because the acquisition time (t
A
) must
start after the conversion result high and low bytes have
been read. This is necessary since activating and deactivat-
ing the digital outputs (DB0/DB7–DB8/DB12) causes cur-
rent fluctuations in the ADC12451’s internal DV
CC
lines.
This generates digital noise which couples into the capaci-
tive ladder that stores the analog input voltage. Therefore,
the time interval between the rising edge of EOC and the
second read is inappropriate for analog input voltage acqui-
sition.
When WR is used to start a conversion with AZ low the
Auto-Zero cycle is inserted before the acquisition window. In
this method the acquisition window is internally controlled
by the ADC12451 and lasts for approximately 7 clock peri-
ods. Since the acquisition window needs to be at least
3.5
m
s at all times, when using Auto-Zero the maximum
clock frequency is limited to 2 MHz. The zero error with the
Auto-Zero cycle is production tested at a clock frequency of
1.75 MHz. This accommodates easy switching between a
conversion with the Auto-Zero cycle (f
CLK
e
1.75 MHz) and
without (f
CLK
e
3.5 MHz) as shown in Figure 5.
TL/H/11025–22
FIGURE 5. Switching between a Conversion with and
without Auto-Zero when Using WR Control
3.3 INPUT CURRENT
Because the input network of the ADC12451 is made up of
a switch and a network of capacitors a charging current will
flow into or out of (depending on the input voltage polarity)
of the analog input pin (V
IN
) on the start of the analog input
sampling period. The peak value of this current will depend
on the actual input voltage applied and the source resist-
ance.
3.4 NOISE
The leads to the analog input pin should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to this input can cause er-
rors. Input filtering can be used to reduce the effects of
these noise sources.
14
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