參數(shù)資料
型號(hào)： ADC12451883
廠商： National Semiconductor Corporation
英文描述： Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
中文描述： 動(dòng)態(tài)息審查自校準(zhǔn)12位帶符號(hào)的A / D轉(zhuǎn)換器的采樣保持電路
文件頁(yè)數(shù)： 4/18頁(yè)
文件大?。?/td> 311K
代理商： ADC12451883
Digital and DC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e a
5.0V, V
b
e b
5.0V, V
REF
e a
5.0V, and f
CLK
e
3.5 MHz unless
otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
;
all other limits T
A
e
T
J
e
25
§
C. (Notes 6 and 7)
Symbol
Parameter
Condition
Typical
(Note 9)
Limit
Units
(Limit)
(Note 10, 19)
V
IN(1)
Logical ‘‘1’’ Input Voltage for
All Inputs except CLK IN
V
CC
e
5.25V
2.0
V(min)
V
IN(0)
Logical ‘‘0’’ Input Voltage for
All Inputs except CLK IN
V
CC
e
4.75V
0.8
V(max)
I
IN(1)
Logical ‘‘1’’ Input Current
V
IN
e
5V
0.005
1
m
A(max)
I
IN(0)
V
T
a
Logical ‘‘0’’ Input Current
V
IN
e
0V
b
0.005
b
1
m
A(max)
CLK IN Positive-Going
Threshold Voltage
2.8
2.7
V(min)
V
T
b
CLK IN Negative-Going
Threshold Voltage
2.1
2.3
V(max)
V
H
CLK IN Hysteresis
[
V
T
a
(min)
b
V
T
b
(max)
]
0.7
0.4
V(min)
V
OUT(1)
Logical ‘‘1’’ Output Voltage
V
CC
e
4.75V:
I
OUT
e b
360
m
A
I
OUT
e b
10
m
A
2.4
4.5
V(min)
V(min)
V
OUT(0)
Logical ‘‘0’’ Output Voltage
V
CC
e
4.75V,
I
OUT
e
1.6 mA
0.4
V(max)
I
OUT
TRI-STATE
é
Output Leakage
Current
V
OUT
e
0V
b
0.01
b
3
m
A(max)
V
OUT
e
5V
0.01
3
m
A(max)
I
SOURCE
Output Source Current
V
OUT
e
0V
b
20
b
6.0
mA(min)
I
SINK
Output Sink Current
V
OUT
e
5V
20
8.0
mA(min)
DI
CC
DV
CC
Supply Current
CS
e
‘‘1’’
1
2.5
mA(max)
AI
CC
I
b
AV
CC
Supply Current
V
b
Supply Current
CS
e
‘‘1’’
2.8
10
mA(max)
CS
e
‘‘1’’
2.8
10
mA(max)
AC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e a
5.0V, V
b
e b
5.0V, t
r
e
t
f
e
20 ns unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
;
all other limits T
A
e
T
J
e
25
§
C. (Notes 6 and 7)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limit
Units
(Limit)
(Note 10, 19)
f
CLK
Clock Frequency
MHz
0.5
6.0
MHz(min)
MHz(max)
3.5
Clock Duty Cycle
50
%
40
60
%(min)
%(max)
t
C
Conversion Time using WR
to start a Conversion
27(1/f
CLK
)
27(1/f
CLK
)
a
250 ns
(max)
f
CLK
e
3.5 MHz, AZ
e
‘‘1’’
7.7
7.95
m
s(max)
f
CLK
e
1.75 MHz, AZ
e
‘‘0’’
15.4
15.65
m
s(max)
t
C
Conversion Time using S/H
to start a Conversion
AZ
e
‘‘1’’
34(1/f
CLK
)
34(1/f
CLK
)
a
250 ns
(max)
f
CLK
e
3.5 MHz, AZ
e
‘‘1’’
9.7
9.95
m
s(max)
4
相關(guān)PDF資料
PDF描述
ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold(可自行校對(duì)的12位帶采樣和保持功能的A/D轉(zhuǎn)換器)
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ADC12451CIJ Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
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ADC1251CMJ Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
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