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ADE7763
REGISTERS
Table 9. Summary of Registers by Address
Address
Name
0x01
WAVEFORM
Rev. A | Page 47 of 56
Descr
Wavef
wavef
signal.
selecte
Sampl
Active
time in
section.
Same a
follow
Line A
power
numbe
Appar
this read-only re
Same as the VAENERGY register, except that the register is reset to 0
following a read operation.
Line Accumulation Apparent Energy Register. The instantaneous real
power is accumulated in this read-only register over the LINECYC
number of half line cycles.
Mode Register. This is a 16-bit register through which most of the
ADE7763’s functionality is accessed. Signal sample rates, filter enabling,
and calibration modes are selected by writing to this register. The
contents can be read at any time—see the Mode Register (0X09) section.
Interrupt Enable Register. ADE7763 interrupts can be deactivated at any
time by setting the corresponding bit in this 16-bit enable register to
Logic 0. The status register continues to detect an interrupt event even if
disabled; however, the IRQ output is not activated—see the Interru ts
section.
Interrupt Status Register. This is a 16-
R/W
R
No. Bits
24
Default
0x0
Type
1
S
iption
orm Register. This read-only register contains the sampled
orm data from either Channel
The data source and the length of the waveform registers are
d by Bits 14 and 13 in the mode register—see the Channel 1
ing and Channel 2 Sampling sections.
Energy Register. Active power is accumulated (integrated) over
this 24-bit, read-only register—see the Energy Calculation
1, Channel 2, or the active power
0x02
AENERGY
R
24
0x0
S
0x03
RAENERGY
R
24
0x0
S
s the active energy register, except that the register is reset to 0
ing a read operation.
ccumulation Active Energy Register. The instantaneous active
is accumulated in this read-only register over the LINECYC
r of half line cycles.
ent Energy Register. Apparent power is accum
gister.
0x04
LAENERGY
R
24
0x0
S
0x05
VAENERGY
R
24
0x0
U
ulated over time in
0x06
RVAENERGY
R
24
0x0
U
0x07
LVAENERGY
R
24
0x0
U
0x08
0x09
RESERVED
MODE
R/W
16
0x000C
U
0x0A
IRQEN
R/W
16
0x40
U
0x0B
STATUS
R
16
0x0
bit read-only register that contains
information regarding the source of ADE7763 interrupts—see the
Interrupts section.
Same as the interrupt status register, except that the register contents
are reset to 0 (all flags cleared) after a read operation.
Channel 1 Offset Adjust. Bit 6 is not used. Writing to Bits 0 to 5 allows
offsets on Channel 1 to be removed—see the Analog Inputs and CH1OS
Register sections. Writing Logic 1 to the MSB of this register enables the
digital integrator on Channel 1; writing Logic 0 disables the integrator.
The default value of this bit is 0.
Channel 2 Offset Adjust. Bits 6 and 7 are not used. Writing to Bits 0 to 5 of
this register allows offsets on Channel 2 to be removed—see the Analog
Inputs section. Note that the CH2OS register is inverted. To apply a
positive offset, a negative number is written to this register.
PGA Gain Adjust. This 8-bit register is used to adjust the gain selection for
the PGA in Channels 1 and 2—see the Analog Inputs section.
Phase Calibration Register. The phase relationship between Channel 1
and 2 can be adjusted by writing to this 6-bit register. The valid content
of this twos complement register is between 0x1D to 0x21. At the line
frequency of 60 Hz, this ranges from –2.06° to +0.7°—see the Phase
Compensation section.
Active Power Offset Correction. This 16-bit register allows small offsets in
the active power calculation to be removed—see the Active Power
Calculation section.
U
0x0C
RSTSTATUS
R
16
0x0
U
0x0D
CH1OS
R/W
8
0x00
S
*
0x0E
CH2OS
R/W
8
0x0
S
*
0x0F
GAIN
R/W
8
0x0
U
0x10
PHCAL
R/W
6
0x0D
S
0x11
APOS
R/W
16
0x0
S