參數(shù)資料
型號(hào)： ADF4158CCPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/36頁(yè)
文件大?。?/td> 0K
描述： IC FRACTION N FREQ SYNT 24LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類型： 分?jǐn)?shù) N 合成器（RF）
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 2:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 6.1GHz
除法器/乘法器： 是/是
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-WQ（4x4）
包裝： 帶卷 (TR)
Data Sheet
ADF4158
Rev. G | Page 3 of 36
REVISION HISTORY
3/14—Rev. F to Rev. G
Changes to Timeout Interval Section...........................................27
2/14—Rev. E to Rev. F
Changed CKJ to CLK, Table 3 .........................................................6
Changed VDD to VDD Parameter to DVDD to AVDD Parameter,
Table 4.................................................................................................7
Changes to 25-Bit Fixed Modulus Section...................................11
Changes to Figure 22 ......................................................................14
Added Σ-Δ Modulator Mode Section...........................................21
Changed 12-Bit Clock Divider Value Section to 12-Bit CLK2
Divider Value Section .....................................................................21
Changes to Clock Divider (DIV) Mode, 12-Bit CLK2 Divider
Value Section, and Figure 27..........................................................21
Changes to Frequency Deviation Section and Timeout Interval
Section ..............................................................................................27
Changes to FMCW Radar Ramp Settings Worked Example
Section ..............................................................................................28
Added External Control of Ramp Steps Section.........................30
Changes to Figure 42 ......................................................................30
Changes to Interrupt Modes and Frequency Readback
Section ..............................................................................................31
Added Fast Lock Mode Section.....................................................32
Changes to Fast Lock Timer and Register Sequences Section,
Fast Lock Example Section, and Fast Lock: Loop Filter Topology
Section ..............................................................................................32
3/13—Rev. D to Rev. E
Changes to Figure 7, Figure 8, Figure 9, and Figure 10................9
Changes to Figure 22 ......................................................................14
Changes to Negative Bleed Current Section, Readback to
MUXOUT Section, and Figure 27 ................................................21
Changes to Figure 28 ......................................................................22
Changes to FMCW Radar Ramp Settings Worked Example
Section ..............................................................................................27
6/12—Rev. C to Rev. D
Changes to Table 3 and Figure 3 .....................................................6
Added Figure 4; Renumbered Sequentially ...................................6
Added Negative Bleed Current Section........................................21
Changes to Figure 27 ......................................................................21
12/11—Rev. B to Rev. C
Changes to Features Section ............................................................1
Changes to Figure 6 Caption to Figure 9 Caption ........................9
Changes to Figure 11 ......................................................................10
Changes to Figure 19 ......................................................................12
Changes to Figure 20 ......................................................................13
Changed 12-Bit MOD Divider Section to 12-Bit CLK1 Divider
Section ..............................................................................................17
Changes to 12-Bit CLK1 Divider Section .....................................17
Changes to Figure 24 ......................................................................18
Changes to Delay Clock Select Section and Figure 29 ...............24
Changes to Timeout Interval Section...........................................27
Changes to FMCW Radar Ramp Settings Worked Example
Section ..............................................................................................28
Changes to Delayed Start, Example Section and Delay Between
Ramps, Example Section ................................................................29
Changes to Fast-Lock Timer and Register Sequences Section
and Fast Lock: An Example Section .............................................32
Changes to Ordering Guide...........................................................35
Added Automotive Products Section ...........................................35
9/11—Rev. A to Rev. B
Changes to Noise Characteristics Parameter.................................3
7/11—Rev. 0 to Rev. A
Changes to Figure 21 ......................................................................13
Changes to Figure 25 ......................................................................19
Changes to 12-Bit Clock Divider Value Section .........................20
Changes to Figure 28 ......................................................................22
Changes to FMCW Radar Ramp Settings Worked Example
Section ..............................................................................................26
Added Ramp Programming Sequence Section, and added
Other Waveforms Heading ............................................................27
Changes to Figure 36 ......................................................................28
Added Ramp Complete Signal to Muxout Section and changes
to Figure 40 ......................................................................................29
Added Figure 42; Renumbered Sequentially...............................30
Changes to Figure 45 ......................................................................31
Changes to Figure 46 ......................................................................33
4/10—Revision 0: Initial Version
相關(guān)PDF資料
PDF描述
X9409WV24-2.7T1 IC XDCP QUAD 64-TAP 10K 24-TSSOP
X9409WS24T1 IC XDCP QUAD 64-TAP 10K 24-SOIC
VE-B5Z-MU-S CONVERTER MOD DC/DC 2V 80W
X9409WS24IT1 IC XDCP QUAD 64-TAP 10K 24-SOIC
VE-B5Y-MU-S CONVERTER MOD DC/DC 3.3V 132W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADF4158WCCPZ 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:分?jǐn)?shù) N 合成器（RF） PLL:是 輸入:CMOS，TTL 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大值:6.1GHz 分頻器/倍頻器:是/是 電壓 - 電源:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-WFQFN 裸露焊盤 供應(yīng)商器件封裝:24-LFCSP-WQ（4x4） 標(biāo)準(zhǔn)包裝:1
ADF4158WCCPZ-RL7 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
ADF4159 制造商:AD 制造商全稱:Analog Devices 功能描述:Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer
ADF4159CCPZ 制造商:Analog Devices 功能描述:Fractional-N Frequency Synthesizer 24-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:DIRECT MODULATION/FAST WAVEFORM GENERATING, 13 GHZ, FRACTION - Trays 制造商:Analog Devices 功能描述:IC PLL FREQ SYNTHESIZER 24LFCSP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL
ADF4159CCPZ-RL7 制造商:Analog Devices 功能描述:Fractional-N Frequency Synthesizer 24-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:13GHZ FAST RAMP DIRECT MOD FRAC N PLL - Tape and Reel 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*