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參數(shù)資料
| 型號： | ADF4158CCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACTION N FREQ SYNT 24LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 分數(shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 6.1GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-WQ（4x4） |
| 包裝： | 帶卷 (TR) |
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ADF4158
Data Sheet
Rev. G | Page 30 of 36
The following example explains how to set up and use this
function.
Example
fOUT = 5790 MHz
fDEV = 100 kHz
Number of steps = 50
Duration of a single step = 10 μs
Ramp mode must be either triangular (Register R3, DB[11:10]
= 01) or single ramp burst (Register R3, DB[11:10] = 11).
In the first case, the generated frequency range is calculated as
follows:
Δf = fDEV × (Number of Steps + 2) × (Number of Steps + 1)/2
= 132.6 MHz
In the second case, the generated frequency range is calculated
as follows:
Δf = fDEV × (Number of Steps + 1) × Number of Steps/2
= 127.5 MHz
The timer is set in the same way as for its linear ramps
described in the Waveform Generation section.
Activation of the parabolic ramp is achieved by setting Bit DB28
in Register R5 to 1.
Next the counter reset (DB3 in Register R3) should be set first
to 1 and then to 0.
Eventually, the ramp must be activated as described in the
Ramp Complete Signal to MUXOUT
Ramp complete signal on MUXOUT is shown in Figure 41.
08
728
-10
0
TIME
V
O
L
T
AG
E
F
RE
Q
UE
NC
Y
Figure 41. Ramp Complete Signal on MUXOUT
To activate this function DB[30:27] = 1111 in Register 0 and
DB[25:21] = 00011 in Register 4.
EXTERNAL CONTROL OF RAMP STEPS
The internal ramp clock can be bypassed and each step can be
triggered by a pulse on the TXDATA pin. This allows for more
transparent control of each step. Enable this feature by setting
Bit DB29 in Register R5 to 1.
F
RE
Q
UE
NC
Y
TIME
TXDATA
RFOUT
V
O
LTA
G
E
TIME
08
728
-14
8
Figure 42. External Control of Ramp Steps
Interrupt Modes and Frequency Readback
Interrupt modes are triggered from the rising edge of TXDATA.
Depending on the settings of DB[27:26] in Register R5, the
modes in Table 7 are activated.
Table 7. Interrupt Modes
Mode
Action
DB[27:26] = 00
Interrupt is off
DB[27:26] = 01
Interrupt on TXDATA, sweep continues
DB[27:26] = 11
Interrupt on TXDATA, sweep stops
When an interrupt takes place, the data consisting of the INT
and FRAC values can be read back via MUXOUT. The data is
made up of 37 bits, 12 of which represent the INT value and 25
the FRAC value.
The idea of frequency readback is shown in Figure 43.
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| ADF4158WCCPZ | 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:分數(shù) N 合成器（RF） PLL:是 輸入:CMOS，TTL 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/無 頻率 - 最大值:6.1GHz 分頻器/倍頻器:是/是 電壓 - 電源:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-WFQFN 裸露焊盤 供應(yīng)商器件封裝:24-LFCSP-WQ（4x4） 標準包裝:1 |
| ADF4158WCCPZ-RL7 | 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4159 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer |
| ADF4159CCPZ | 制造商:Analog Devices 功能描述:Fractional-N Frequency Synthesizer 24-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:DIRECT MODULATION/FAST WAVEFORM GENERATING, 13 GHZ, FRACTION - Trays 制造商:Analog Devices 功能描述:IC PLL FREQ SYNTHESIZER 24LFCSP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL |
| ADF4159CCPZ-RL7 | 制造商:Analog Devices 功能描述:Fractional-N Frequency Synthesizer 24-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:13GHZ FAST RAMP DIRECT MOD FRAC N PLL - Tape and Reel 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL |
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