VTUNE
參數(shù)資料
型號(hào)： ADF4193BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/32頁(yè)
文件大?。?/td> 0K
描述： IC PLL FREQ SYNTHESIZER 32LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率合成器，RF
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 2:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 3.5GHz
除法器/乘法器： 是/是
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 551 (CN2011-ZH PDF)
配用： EVAL-ADF4193EBZ2-ND - BOARD EVALUATION EB2 FOR ADF4193
EVAL-ADF4193EBZ1-ND - BOARD EVALUATION EB1 FOR ADF4193
Data Sheet
ADF4193
Rev. F | Page 9 of 32
05328-040
TIME (
s)
(V)
–1
0
1
2
3
4
5
9
8
7
6
5
4
3
2
1
0
VTUNE
CPOUT+
CPOUT–
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
FREQUENCY LOCK IN WIDE BW MODE @ 4
s.
Figure 10. VTUNE Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz with Sirenza 1843T VCO
05328-008
TIME (
s)
PHASE
ERROR
(Degrees)
–5
0
5
10
15
20
25
30
35
40
–50
50
40
30
20
10
0
–10
–20
–30
–40
45
+25
°C
+85
°C
–40
°C
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD WITH AD8302
PHASE DETECTOR.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
PEAK PHASE ERROR < 5
° @ 17.8s
Figure 11. Phase Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz (VTUNE 1.8 V to 3.7 V with Sirenza 1843T VCO)
05328-
012
CPOUT + / CPOUT – VOLTAGE (V)
I CP
(
mA)
M
IS
M
AT
CH
(
%)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–8
–6
–4
–2
0
2
4
6
8
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
5.0
ICPOUT + P, ICPOUT – P
CHARGE PUMP MISMATCH (%)
NORMAL OPERATING RANGE
ICPOUT + N, ICPOUT – N
IUP = | ICPOUT + P | + | ICPOUT – N |
IDOWN = | ICPOUT – P | + | ICPOUT + N |
Figure 12. Differential Charge Pump Output Compliance Range and
Charge Pump Mismatch with VP1 = VP2 = 5 V
05328-041
TIME (
s)
(V)
–1
0
1
2
3
4
5
9
8
7
6
5
4
3
2
1
0
VTUNE
CPOUT–
CPOUT+
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
FREQUENCY LOCK IN WIDE BW MODE @ 5
s.
Figure 13. VTUNE Settling Transient for a 75 MHz Jump Down from 1893 MHz to
1818 MHz, the Bottom of the Allowed Tuning Range with the Sirenza 1843T VCO
05328-009
TIME (
s)
PHASE
ERROR
(Degrees)
–5
0
5
10
15
20
25
30
35
40
–50
50
40
30
20
10
0
–10
–20
–30
–40
45
+25
°C
+85
°C
–40
°C
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD WITH AD8302
PHASE DETECTOR.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
PEAK PHASE ERROR < 5
° @ 19.2s
Figure 14. Phase Settling Transient for a 75 MHz Jump from 1893 MHz to
1818 MHz (VTUNE = 3.7 V to 1.8 V with Sirenza 1843T VCO)