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參數(shù)資料
| 型號(hào)： | ADF4193BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
| 配用： | EVAL-ADF4193EBZ2-ND - BOARD EVALUATION EB2 FOR ADF4193 EVAL-ADF4193EBZ1-ND - BOARD EVALUATION EB1 FOR ADF4193 |
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ADF4193
Data Sheet
Rev. F | Page 12 of 32
The value of MOD is chosen to give the desired channel step
with the available reference frequency. Thereafter, program the
INT and FRAC words for the desired RF output frequency. See
the Worked Example section for more information.
PFD and Charge Pump
The PFD takes inputs from the R divider and N divider and
produces up and down outputs with a pulse width difference
proportional to the phase difference between the inputs. The
charge pump outputs a net up or down current pulse of a width
equal to this difference, to pump up or pump down the voltage
that is integrated onto the loop filter, which in turn increases or
decreases the VCO output frequency. If the N divider phase lags
the R divider phase, a net up current pulse is produced that
increases the VCO frequency (and thus the phase). If the N
divider phase leads the R divider edge, then a net down pulse is
produced to reduce the VCO frequency and phase. Figure 23 is
a simplified schematic of the PFD and charge pump. The charge
pump is made up of an array of 64 identical cells, each of which
is fully differential. All 64 cells are active during fast lock, but
only one is active during normal operation. Because a single-
ended control voltage is required to tune the VCO, an on-chip,
differential-to-single-ended amplifier is provided for this purpose.
In addition, because the phase-lock loop only controls the
differential voltage generated across the charge pump outputs,
an internal common-mode feedback (CMFB) loop biases the
charge pump outputs at a common-mode voltage of approximately
2 V.
05328-019
CLR
Q
D
R DIVIDER
N DIVIDER
CHARGE
PUMP
ARRAY
[64:1]
CMFB
EN[64:1]
CLR
Q
D
CPOUT+
CPOUT–
Figure 23. PFD and Differential Charge Pump Simplified Schematic
Differential Charge Pump
The charge pump cell (see Figure 24) has a fully differential
design for best up-to-down current matching. Good matching
is essential to minimize the phase offset created when switching
the charge pump current from its high value (in fast lock mode)
to its nominal value (in normal mode).
To pump up, the up switches are on and PMOS current is
sourced out through CPOUT+; this increases the voltage on the
external loop filter capacitors connected to CPOUT+. Similarly,
the NMOS current sink on CPOUT decreases the voltage on the
external loop filter capacitors connected to CPOUT. Therefore,
the differential voltage between CPOUT+ and CPOUT increases.
To pump down, PMOS current sources out through CPOUT and
NMOS current sinks in through CPOUT+, which decreases the
(CPOUT+, CPOUT) differential voltage. The charge pump up/
down matching is improved by an order of magnitude over the
conventional single-ended charge pump that depended on the
matching of two different device types. The up/down matching
in this structure depends on how a PMOS matches a PMOS and
an NMOS matches an NMOS.
05328-035
VBIAS P
P
N
UP
DOWN
UP
VBIAS N
CPOUT+
CPOUT–
Figure 24. Differential Charge Pump Cell with External Loop Filter Components
Fast Lock Timeout Counters
Timeout counters, clocked at one quarter the PFD reference
frequency, are provided to precisely control the fast locking
operation (see Figure 25). Whenever a new frequency is
programmed, the fast lock timers start and the PLL locks into
wide BW mode with the 64 identical 100 A charge pump cells
active (6.4 mA total). When the ICP counter times out, the
charge pump current is reduced to 1× by deselecting cells in
binary steps over the next six timer clock cycles, until just one
100 A cell is active. The charge pump current switching from
6.4 mA to 100 A equates to an 8-to-1 change in loop bandwidth.
The loop filter must be changed to ensure stability when this
happens. That is the job of the SW1, SW2, and SW3 switches. The
application circuit (shown in Figure 36) shows how they can be
used to reconfigure the loop filter time constants. The application
circuits close to short out external loop filter resistors during fast
lock and open when their counters time out to restore the filter
time constants to their normal values for the 100 A charge
pump current. Because it takes six timer clock cycles to reduce
the charge pump current to 1×, it is recommended that both
switch timers be programmed to the value of the ICP timer + 7.
05328-
036
SW1/SW2
TIMEOUT
COUNTER
SW3
TIMEOUT
COUNTER
ICP
TIMEOUT
COUNTER
EN[64:1]
÷4
START
FPFD
SW3
AOUT
SW2
SWGND
SW1
WRITE
TO R0
CHARGE PUMP
ENABLE LOGIC
Figure 25. Fast Lock Timeout Counters
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| ADF4193BCPZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ADF4193BCPZ-RL7 | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ADF4193SP1BCPZ | 制造商:Analog Devices 功能描述: |
| ADF4193SP1BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
| ADF4193SP2BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
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