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參數(shù)資料
| 型號： | ADN2812ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
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ADN2812
Data Sheet
Rev. E | Page 12 of 28
TERMINOLOGY
INPUT SENSITIVITY AND INPUT OVERDRIVE
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 12. For sufficiently large positive input voltage,
the output is always at Logic Level 1 and, similarly for negative
inputs, the output is always at Logic Level 0. However, the
output transitions between Logic Level 1 and Logic Level 0
are not at precisely defined input voltage levels but occur over
a range of input voltages. Within this range of input voltages,
the output might be either 1 or 0, or it might even fail to attain
a valid logic state. The width of this zone is determined by the
input voltage noise of the quantizer. The center of the zone is
the quantizer input offset voltage. Input overdrive is the magni-
tude of signal required to guarantee the correct logic level with
1 × 1010 confidence level.
04228-
012
NOISE
OUTPUT
INPUT (V p-p)
OFFSET
OVERDRIVE
SENSITIVITY
(2
OVERDRIVE)
1
0
Figure 12. Input Sensitivity and Input Overdrive
SINGLE-ENDED VS. DIFFERENTIAL
AC coupling is typically used to drive the inputs to the quan-
tizer. The inputs are internally dc biased to a common-mode
potential of ~2.5 V. Driving the ADN2812 single-ended and
observing the quantizer input with an oscilloscope probe at the
point indicated in Figure 13 show a binary signal with an average
value equal to the common-mode potential and instantaneous
values both above and below the average value. It is convenient
to measure the peak-to-peak amplitude of this signal and call
the minimum required value the quantizer sensitivity. Referring
to Figure 13, because both positive and negative offsets need to
be accommodated, the sensitivity is twice the overdrive. The
ADN2812 quantizer typically has 6 mV p-p sensitivity.
04228-
013
SCOPE
PROBE
PIN
50Ω
3kΩ
2.5V
50Ω
VREF
ADN2812
QUANTIZER
+
–
10mV p-p
VREF
Figure 13. Single-Ended Sensitivity Measurement
While driving the ADN2812 differentially (see Figure 14), sen-
sitivity seems to improve from observing the quantizer input
with an oscilloscope probe. This is an illusion caused by the use
of a single-ended probe. A 5 mV p-p signal appears to drive the
ADN2812 quantizer. However, the single-ended probe measures
only half the signal. The true quantizer input signal is twice
this value because the other quantizer input is a complementary
signal to the signal being observed.
04228-
014
SCOPE
PROBE
PIN
50Ω
3kΩ
2.5V
50Ω
VREF
QUANTIZER
+
–
NIN
5mV p-p
VREF
5mV p-p
VREF
Figure 14. Differential Sensitivity Measurement
LOS RESPONSE TIME
Loss of signal (LOS) response time is the delay between
removal of the input signal and indication of LOS at the LOS
output, Pin 22. When the inputs are dc-coupled, the LOS assert
time of the AD2812 is 500 ns typically and the deassert time is
400 ns typically. In practice, the time constant produced by the
ac coupling at the quantizer input and the 50 on-chip input
termination determines the LOS response time.
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