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| 型號： | ADN2812ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR），多路復用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
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ADN2812
Data Sheet
Rev. E | Page 16 of 28
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
The ADN2812 acquires frequency from the data over a range of
data frequencies from 12.3 Mb/s to 2.7 Gb/s. The lock detector
circuit compares the frequency of the VCO and the frequency
of the incoming data. When these frequencies differ by more
than 1000 ppm, LOL is asserted. This initiates a frequency
acquisition cycle. The VCO frequency is reset to the bottom
of its range, which is 12.3 MHz. The frequency detector then
compares this VCO frequency and the incoming data frequency
and increments the VCO frequency, if necessary. Initially, the
VCO frequency is incremented in large steps to aid fast acquisi-
tion. As the VCO frequency approaches the data frequency, the
step size is reduced until the VCO frequency is within 250 ppm
of the data frequency, at which point LOL is deasserted.
Once LOL is deasserted, the frequency-locked loop is turned
off. The PLL/DLL pulls in the VCO frequency the rest of the
way until the VCO frequency equals the data frequency.
The frequency loop requires a single external capacitor between
CF2 and CF1 (Pin 14 and Pin 15). A 0.47 F ± 20%, X7R ceramic
chip capacitor with <10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 F capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 F capacitor should be greater than 300 M.
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN), which
are internally terminated with 50 to an on-chip voltage reference
(VREF = 2.5 V typically). The inputs are typically accoupled
externally, although dc coupling is possible as long as the input
common-mode voltage remains above 2.5 V (see Figure 28,
Figure 29, and Figure 30). Input offset is factory trimmed to
achieve better than 6 mV typical sensitivity with minimal drift.
The limiting amplifier can be driven differentially or single-
ended.
SLICE ADJUST
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or
duty cycle distortion by applying a differential voltage input of
up to ±0.95 V to the SLICEP/SLICEN inputs. If no adjustment
of the slice level is needed, SLICEP/SLICEN should be tied to
VEE. The gain of the slice adjustment is ~0.1 V/V.
LOS DETECTOR
The receiver front-end LOS detector circuit detects when the
input signal level has fallen below a user-adjustable threshold.
The threshold is set with a single external resistor from Pin 9
(THRADJ) to VEE. The LOS comparator trip point-vs.-resistor
value is illustrated in Figure 5. If the input level to the ADN2812
drops below the programmed LOS threshold, the output of the
LOS detector, LOS (Pin 22), is asserted to a Logic 1. The LOS
detector’s response time is ~500 ns by design but is dominated
by the RC time constant in ac-coupled applications. The LOS
pin defaults to active high. However, by setting Bit CTRLC[2]
to 1, the LOS pin is configured as active low.
Typically, 6 dB of electrical hysteresis is designed into the LOS
detector to prevent chatter on the LOS pin. This means that if
the input level drops below the programmed LOS threshold
causing the LOS pin to assert, the LOS pin is not deasserted
until the input level increases to 6 dB (2×) above the LOS
threshold (see Figure 19).
04228-
019
HYSTERESIS
LOS OUTPUT
INPUT LEVEL
LOS THRESHOLD
t
INP
UT
V
O
LT
A
G
E
(V
DI
F
)
Figure 19. LOS Detector Hysteresis
The LOS detector and the SLICE level adjust can be used simul-
taneously on the ADN2812. This means that any offset added to
the input signal by the SLICE adjust pins does not affect the
LOS detector’s measurement of the absolute input level.
LOCK DETECTOR OPERATION
The lock detector on the ADN2812 has three modes of operation:
normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2812 is a continuous rate CDR that
locks onto any data rate from 12.3 Mb/s to 2.7 Gb/s without the
use of a reference clock as an acquisition aid. In this mode, the
lock detector monitors the frequency difference between the
VCO and the input data frequency and deasserts the loss of
lock signal appearing on LOL (Pin 16) when the VCO is within
250 ppm of the data frequency. This enables the D/PLL, which
pulls the VCO frequency in the remaining amount and also
acquires phase lock. Once locked, if the input frequency error
exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted
and control returns to the frequency loop, which begins a new
frequency acquisition starting at the lowest point in the VCO
operating range, 12.3 MHz. The LOL pin remains asserted until
the VCO locks onto a valid input data stream to within 250 ppm
frequency error. This hysteresis is shown in Figure 20.
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