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| 型號(hào)： | ADN2812ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
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Data Sheet
ADN2812
Rev. E | Page 17 of 28
04228-
020
LOL
0
–250
250
1000
fVCO ERROR
(ppm)
–1000
1
Figure 20. Transfer Function of LOL
LOL Detector Operation Using a Reference Clock
(REFCLK Mode)
In REFCLK mode, a reference clock is used as an acquisition
aid to lock the ADN2812 VCO. Lock to reference mode is
enabled by setting CTRLA[0] to 1. The user also needs to
write to the CTRLA[7:6] and CTRLA[5:2] bits in order to set
the reference frequency range and the divide ratio of the data
rate with respect to the reference frequency. For more details,
see the Reference Clock (Optional) section. In this mode, the
lock detector monitors the difference in frequency between
the divided down VCO and the divided down reference clock.
The loss of lock signal, which appears on LOL (Pin 16), is deas-
serted when the VCO is within 250 ppm of the desired frequency.
This enables the D/PLL, which pulls the VCO frequency in the
remaining amount with respect to the input data and also acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss of lock signal is reasserted and
control returns to the frequency loop, which reacquires with
respect to the reference clock. The LOL pin remains asserted
until the VCO frequency is within 250 ppm of the desired
frequency. This hysteresis is shown in Figure 20.
Static LOL Mode
The ADN2812 implements a static LOL feature, which indicates
if a loss of lock condition has ever occurred and remains asserted,
even if the ADN2812 regains lock, until the static LOL bit is manu-
ally reset. The I2C register bit, MISC[4], is the static LOL bit. If
there is ever an occurrence of a loss of lock condition, this bit is
internally asserted to logic high. The MISC[4] bit remains high
even after the ADN2812 has reacquired lock to a new data rate.
This bit can be reset by writing a 1 followed by 0 to I2C Register
Bit CTRLB[6]. Once reset, the MISC[4] bit remains deasserted
until another loss of lock condition occurs.
Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin
(Pin 16) to become a static LOL indicator. In this mode, the
LOL pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph. The CTRLB[7]
bit defaults to 0. In this mode, the LOL pin operates in the normal
operating mode, that is, it is asserted only when the ADN2812
is in acquisition mode and deasserts when the ADN2812 has
reacquired lock.
HARMONIC DETECTOR
The ADN2812 provides a harmonic detector, which detects
whether the input data has changed to a lower harmonic of the
data rate onto which the VCO is currently locked. For example,
if the input data instantaneously changes from OC-48, 2.488 Gb/s,
to an OC-12, 622.080 Mb/s bit stream, this could be perceived
as a valid OC-48 bit stream because the OC-12 data pattern is
exactly 4× slower than the OC-48 pattern. So, if the change in
data rate is instantaneous, a 101 pattern at OC-12 would be per-
ceived by the ADN2812 as a 111100001111 pattern at OC-48. If
the change to a lower harmonic is instantaneous, a typical CDR
could remain locked at the higher data rate.
The ADN2812 implements a harmonic detector that automati-
cally identifies whether the input data has switched to a lower
harmonic of the data rate onto which the VCO is currently
locked. When a harmonic is identified, the LOL pin is asserted
and a new frequency acquisition is initiated. The ADN2812
automatically locks onto the new data rate, and the LOL pin
is deasserted.
However, the harmonic detector does not detect higher har-
monics of the data rate. If the input data rate switches to a
higher harmonic of the data rate that the VCO is currently
locked onto, the VCO loses lock, the LOL pin is asserted,
and a new frequency acquisition is initiated. The ADN2812
automatically locks onto the new data rate.
The time to detect lock to harmonic is
16,384 × (Td/ρ)
where:
1/Td is the new data rate. For example, if the data rate is
switched from OC-48 to OC-12, then Td= 1/622 MHz.
ρ is the data transition density. Most coding schemes seek
to ensure that ρ = 0.5, for example, PRBS, 8B/10B.
When the ADN2812 is placed in lock to reference mode,
the harmonic detector is disabled.
SQUELCH MODE
Two squelch modes are available with the ADN2812.
Squelch DATAOUT and CLKOUT mode is selected
when CTRLC[1] = 0 (default mode). In this mode, when
the squelch input (Pin 27) is driven to a TTL high state,
both the clock and data outputs are set to the zero state to
suppress downstream processing. If the squelch function
is not required, Pin 27 should be tied to VEE.
Squelch DATAOUT or CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the squelch input is
driven to a high state, the DATAOUT pins are squelched.
When the squelch input is driven to a low state, the CLKOUT
pins are squelched. This is especially useful in repeater appli-
cations, where the recovered clock may not be needed.
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