參數(shù)資料
型號(hào): ADN2817ACPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 36/40頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK/DATA RECOVERY 32-LFCSP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: SONET/SDH
輸入: CML
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.7GHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 788 (CN2011-ZH PDF)
Data Sheet
ADN2817/ADN2818
Rev. E | Page 5 of 40
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Voltage
3.0
3.3
3.6
V
Current
ADN2817
210
247
mA
ADN2818
180
217
mA
OPERATING TEMPERATURE RANGE
40
+85
°C
1
PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2
When ac-coupled, the LOS assert and deassert time is dominated by the RC time constant of the ac coupling capacitor and the 50 input termination of the ADN2817
input stage.
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 1,
unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer Bandwidth
OC-48
548
839
kHz
OC-12
93
137
kHz
OC-3
30
40
kHz
Jitter Peaking
OC-48
0
0.03
dB
OC-12
0
0.03
dB
OC-3
0
0.03
dB
Jitter Generation
OC-48
12 kHz to 20 MHz
0.001
0.003
UI rms
0.02
0.046
UI p-p
OC-12
12 kHz to 5 MHz
0.001
0.004
UI rms
0.01
0.036
UI p-p
OC-3
12 kHz to 1.3 MHz
0.001
0.004
UI rms
0.01
0.023
UI p-p
Jitter Tolerance
223 1 PRBS
OC-48
600 Hz1
92.0
UI p-p
6 kHz1
20.0
UI p-p
100 kHz
7.0
UI p-p
1 MHz1
1.00
UI p-p
20 MHz
0.53
UI p-p
OC-12
30 Hz1
100.0
UI p-p
300 Hz1
44.0
UI p-p
25 kHz
7.35
UI p-p
250 kHz1
1.00
UI p-p
5 MHz
0.52
UI p-p
OC-3
30 Hz1
50.0
UI p-p
300 Hz1
23.5
UI p-p
6500 Hz
6.71
UI p-p
65 kHz1
1.00
UI p-p
130 kHz
0.54
UI p-p
1
Jitter tolerance of the ADN2817/ADN2818 at these jitter frequencies is better than what the test equipment is able to measure.
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