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參數(shù)資料
| 型號(hào)： | ADN2860 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 數(shù)字電位計(jì) |
| 英文描述： | High Bandwidth, CMOS 8-Bit Serial Interface Multiplying D/A Converter; Package: MSOP; No of Pins: 10; Temperature Range: Industrial |
| 中文描述： | 250K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 512 POSITIONS, QCC24 |
| 封裝： | 4 X 4 MM, LFCSP-24 |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大?。?/td> | 1132K |
| 代理商： | ADN2860 |
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Preliminary Technical Data
A more detailed discussion about the RDAC quick commands
can be found in the Operational Overview section of this
document.
OPERATIONAL OVERVIEW
The ADN2860 digital potentiometer is designed to operate as a
true variable resistor. The resistor wiper position is determined
by the RDAC register contents. The RDAC register acts like a
scratch-pad register, allowing unlimited changes of resistance
settings. RDAC register contents can be changed using the
ADN2860’s serial I
2
C interface. The format of the datawords
and commands to program the RDAC registers are discussed in
the RDAC I
C Interface section of this document.
RDAC registers also have a corresponding EEPROM memory
location, which provide non-volatile storage of resistor wiper
position settings. The ADN2860 provides commands to store
the RDAC register contents to their respective EEPROM
memory locations. During subsequent power on sequences, the
RDAC registers will automatically be loaded with the stored
value.
Saving data from an RDAC register to EEPROM memory takes
approximately 25ms and consumes 20mA of current.
In addition to the movement of data between RDAC registers
and EEPROM memory, the ADN2860 provides other shortcut
commands that facilitate the users’ programming needs.
1.
Restore EEPROM setting to RDAC
2.
Save RDAC register contents to EEPROM
3.
Decrement RDAC 6dB (Shift Data Bits Right)
4.
Decrement all RDACs 6dB (Shift All Data Bits Right)
5.
Decrement RDAC one step
6.
Decrement all RDACs one step
7.
Reset EEPROM setting to RDAC
8.
Increment RDAC 6dB (Shift Data Bits Left)
9.
Increment all RDACs 6dB (Shift All Data Bits Left)
10.
Increment RDAC one step
11.
Increment all RDACs one step
Table 4. ADN2860 Shortcut Commands
Linear Increment and Decrement Commands
The increment and decrement commands (#10, #11, #5, #6) are
useful for linear step adjustment applications. These commands
simplify microcontroller software coding by allowing the
controller to just send an increment or decrement command to
the ADN2860. The adjustment can be directed to an individual
RDAC or all three RDACs.
Logarithmic Taper Mode Adjustment (
±
6dB/step)
The ADN2860 accommodates logarithmic taper adjustment of
the RDAC wiper position(s) by shifting the register contents
left/right for increment/decrement operations. Commands 8, 9,
3, and 4 can be used to logarithmically increment or decrement
the wiper positions individually or change all three channel
settings at the same time.
ADN2860
Page 10 of 15
Incrementing the wiper position by +6dB is essentially doubling
the RDAC register value, while decrementing by –6dB is
halving the register content. Internally, the ADN2860 uses a
shift register to shift the bits left and right to achieve a
logarithmic increment or decrement.
Non-ideal
±
6dB step adjustment occurs under certain
conditions. Table 5 illustrates the shifting function on an
individual RDAC register data bits. Each line going down the
table represents a successive shift operation. Note that the left
shift (#10 & #11) commands were modified such that if the data
in the RDAC register is equal to zero, and the data is shifted the
RDAC register is then set to code 1. Similarly, if the data in the
RDAC register is greater than or equal to mid-scale, and the
data is left shifted, the data in the RDAC register is
automatically set to full-scale. This makes the left shift function
as close to a logarithmic adjustment as possible.
The right shift commands (#3 & #4) will be ideal only if the
LSB is a 0 (ideal logarithmic = no error). If the LSB is a 1 then
the right shift function generates a linear half LSB error, which
translates to a number of error bits.
Left Shift
0 0000 0000
0 0000 0001
0 0000 0010
0 0000 0100
0 0000 1000
0 0001 0000
0 0010 0000
0 0100 0000
0 1000 0000
1 0000 0000
1 1111 1111
1 1111 1111
Table 5. RDAC Register Contents After
±
6dB Step Adjustments
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
right shift (#3 & #4) command execution contains an error only
for odd numbers of bits. Even numbers of bits are ideal. The
graph in figure 12 shows a plot of Log_Error
[i.e. 20*Log10(error/code)] for the ADN2860.
Right Shift
1 1111 1111
0 1111 1111
0 0111 1111
0 0011 1111
0 0001 1111
0 0000 1111
0 0000 0111
0 0000 0011
0 0000 0001
0 0000 0000
0 0000 0000
Figure 12. Plot of Log_Error Conformance for Odd Numbers of
Bits Only (Even Numbers of Bits are ideal)
Left
Shift
(+6dB/step)
Right
Shift
(-6dB/step)
REV. PrD
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| ADN2860ACPZ250-RL7 | 功能描述:IC POT DGTL 3CH 250K 24-LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲(chǔ)器類(lèi)型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
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