
Preliminary Technical Data
EEPROM I
2
C Interface Description
S
1
0
1
0
0
A
1
E
E
ADN2860
Page 7 of 15
A
0
0
A
Memory Address
A
Memory Data
A
Memory Data
A/
A
P
Figure 5. EEPROM Write
S
1
0
1
0
0
A
1
E
A
0
E
1
A
Memory Data
A
Memory Data
A
P
Figure 6. EEPROM Current Read
S
Slave Address
W
A
Memory Address
A
S
Slave Address
R
A
Memory Data
A/
A
P
Figure 7. EEPROM Random Read
EEPROM Interface Operation
The 256 bytes of EEPROM memory provided in the ADN2860
are organized into 16 pages of 16 bytes each. The word size of
each memory location is one byte wide.
The I
2
C slave address of the EEPROM is 10100(A1E)(A0E),
where A1E and A0E are external pin programmable address
bits. The two pin programmable address bits allow a total of
four ADN2860 devices to be controlled by a single I
2
C master
bus, each having its own EEPROM.
An internal 8-bit address counter for the EEPROM is
automatically incremented following each read or write
operation. For read operations, the address counter is
incremented after each byte is read, and the counter will rollover
from address location 255 to 0.
For write operations, the address counter will be incremented
after each byte written. The counter rolls-over from the upper
most address of the current page to the lower most address of
the current page. For example, writing two bytes beginning at
address location 31 will cause the counter to roll back to address
location 16 after the first byte is written, and then the address
will increment to 17 after the second byte is written.
EEPROM Write
Each write operation issued to the EEPROM can program 1 byte
to 16 bytes (1 page) of memory. Figure 5 shows the EEPROM
write interface, the number of bytes of data, N, the user wishes
to send to the EEPROM is unrestricted. If more than 16 bytes of
data are sent in a single write operation, the address counter will
rollback to the beginning address, and the previously sent data
will be overwritten.
EEPROM Write-Acknowledge Polling
After each write operation, an internal EEPROM write cycle
begins. During the EEPROM internal write cycle, the I
2
C
interface of the device will be disabled. In order to determine if
the internal write cycle is complete and whether the I
2
C
interface is enabled, interface polling must be executed. I
2
C
interface polling can be conducted by sending a start condition
followed by the EEPROM slave address + desired R/W bit. If
the ADN2860 I
2
C interface responds with an ACK, then the
write cycle is complete and the interface is ready to proceed
with further operations. Otherwise, the I
C interface needs to be
polled again to determine whether the write cycle has been
completed.
EEPROM Read
The ADN2860 EEPROM provides two different read
operations, shown in figures 6 and 7. The number of bytes, N,
read from the EEPROM in a single operation is unrestricted. If
more than 256 bytes are read, the address counter will rollback
to the start address, and data previously read will be read again.
Figure 6 shows the EEPROM Current Read operation. This
operation does not allow an address location to be specified and
reads data beginning at the current address location stored in the
internal address counter.
A random read operation is shown in figure 7. This operation
changes the address counter to the specified memory address by
performing a “dummy write” and then performing a read
operation beginning at the new address counter location.
EEPROM Write Protection
0 Write
Repeated Start
1 Read
(N bytes + Acknowledge)
(N bytes + Acknowledge)
1 Read
0 Write
EEPROM Slave Address
(N bytes + Acknowledge)
EEPROM Slave Address
REV. PrD