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參數(shù)資料
| 型號： | ADN2860 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | High Bandwidth, CMOS 8-Bit Serial Interface Multiplying D/A Converter; Package: MSOP; No of Pins: 10; Temperature Range: Industrial |
| 中文描述： | 250K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 512 POSITIONS, QCC24 |
| 封裝： | 4 X 4 MM, LFCSP-24 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 1132K |
| 代理商： | ADN2860 |
Preliminary Technical Data
ADN2860 ELECTRICAL CHARACTERISTICS 25k, 250k VERSIONS
( V
DD
= 3V to 5.5V and –40C <TA<+85C, unless otherwise noted)
Parameter
Symbol
DYNAMIC CHARACTERISTICS
5, 9
Bandwidth –3dB
BW
Total Harmonic Distortion
THD
W
V
W
Settling Time
t
S
Resistor Noise Spectral Density
e
N_WB
Crosstalk (C
W1
/C
W2
)
C
T
Analog Crosstalk
C
TA
ADN2860
Page 3 of 15
Conditions
Min
Typ
1
Max
Units
V
DD
/V
SS
= +/-2.5 V, R
AB
= 25 k
/
250 k
V
A
=1Vrms, V
B
= 0V, f=1 kHz
V
A
= V
DD
, V
B
=0V, V
W
=0.50% error band,
code 000
H
to 200
H
. R
AB
= 25 k/250 k
R
AB
= 25 k
/
250 k
, T
A
= 25
o
C
V
A
= V
DD
, V
B
= 0V, Measured V
W1
with V
W2
making full scale change, R
AB
= 25 k/250 k
V
DD
= V
A1
= +2.5 V, V
SS
= V
B1
= -2.5 V, Measure
V
W1
with V
W2
= 5V p-p @ f = 1kHz, Code1 = 200
H
,
Code 2 = 3FF
H
, R
AB
= 25 k
/ 250 k
125/12
0.05
kHz
%
4 / 36
20 / 64
90/21
μs
nV
√
Hz
nV-s
-81/-62
dB
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency
t
BUF
Bus free time between
STOP & START
t
HD;STA
Hold Time (repeated START)
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time For START Condition t
5
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
R
Rise Time of both SDA & SCL signals
t
F
Fall Time of both SDA & SCL signals
t
SU;STO
Setup time for STOP Condition
NOTES:
1.
Typical represent average readings at +25°C, V
DD
= +5V.
2.
Resistor position non-linearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit.
3.
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0V.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.
4.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5.
Guaranteed by design and not subject to production test.
6.
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value
results in the minimum overall power consumption.
7.
PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
8.
All dynamic characteristics use V
DD
= +5V.
9.
See timing diagram for location of measured values.
10.
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C and +85°C, typical endurance at 25°C is 700,000 cycles.
11.
Retention lifetime equivalent at junction temperature (T
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction
temperature.
The ADN2860 contains 21,035 transistors. Die size: 88.2 mil x 87.0 mil, 7673 sq. mil.
Specifications Subject to Change without Notic
f
SCL
t
1
t
2
t
3
t
4
After this period the first clock pulse is generated
0
1.3
600
1.3
0.6
600
100
600
400
50
900
300
300
KHz
μs
ns
μs
μs
ns
ns
ns
ns
ns
ns
t
6
t
7
t
8
t
9
t
10
REV. PrD
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