參數(shù)資料
型號: ADN2860
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字電位計
英文描述: High Bandwidth, CMOS 8-Bit Serial Interface Multiplying D/A Converter; Package: MSOP; No of Pins: 10; Temperature Range: Industrial
中文描述: 250K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 512 POSITIONS, QCC24
封裝: 4 X 4 MM, LFCSP-24
文件頁數(shù): 11/15頁
文件大?。?/td> 1132K
代理商: ADN2860
Preliminary Technical Data
Using Additional Internal Nonvolatile EEPROM
The ADN2860 contains additional internal user EEPROM for
saving constants and other data. The user EEPROM I
2
C
dataword follows the same format as the general purpose
EEPROM memory shown in figures 5 and 6. User EEPROM
memory addresses are shown at the bottom of table 2.
To support the use of multiple EEPROM modules on a single
I
2
C bus, the ADN2860 features two external addressing pins,
pins 21 and 22 (A1_EE and A0_EE) to manually set the address
of the EEPROM included with the ADN2860. This feature
ensures that the correct EEPROM memory is accessed when
using multiple memory modules on a single I
2
C bus.
Digital Input/Output Configuration
All digital inputs are ESD protected. Digital inputs are high
impedence and can be driven directly from most digital sources.
Active at logic low,
RESET
and
WP
should be biased to V
DD
if
they are not used. There are no internal pull-up resistors present
on any of the digital input pins of the ADN2860. As a result,
pull-up resistors are needed if these functions are not used.
ESD protection of the digital inputs is shown in figure 13.
ADN2860
Page 11 of 15
INPUT
WP
V
DD
GND
300
Figure 13. Equivalent WP Input Protection
Multiple Devices On One Bus
Figure 14 shows four ADN2860 devices on the same serial bus.
Each has a different slave address since the state of their AD0
and AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently.
R
p
S
D
A
D
0
A
S
C
L
A
D
1
M
A
S
T
E
R
SDA
SCL
R
p
+
5
V
S
D
A
S
C
A
D
L
A
D
1
0
S
D
A
S
C
L
A
D
A
D
1
0
SDA SCL
AD1
AD0
V
D
D
V
D
D
V
D
D
Figure 14. Multiple ADN2860 Devices on a Single Bus
Level Shift for Bi-Directional Communication
While most old systems may be operating at one voltage, a new
component may be optimized at another. When two systems
transmit the same signal at two different voltages, proper level
shifting is required.
In some instances, for example, a 3.3V EEPROM memory
module may be used along with a 5V digital potentiometer. A
level shifting scheme is required in order to enable bi-directional
communication between the two devices.
VDD1= 3.3V
3.3V
E2PROM
5V
ADN2860
SDA1
SCL1
SDA2
SCL2
Rp
Rp
R
p
Rp
VDD2= 5V
D
D
S
S
G
G
M1
M
2
Figure 15. Level Shifting for different voltage devices on an I2C
bus
Figure 15 shows one of many possible techniques to properly
level shift signals between two devices. M1 and M2 can be N-
channel FETs (2N7002). If V
DD
falls below 2.5V, M1 and M2
should be low threshold N-channel FETs (FDV301N).
Terminal Voltage Operation Range
The ADN2860 positive V
DD
and negative V
SS
power supply
inputs define the boundary conditions for proper 2-terminal
programmable resistance operation. Supply signals on terminals
W and B that exceed V
DD
or V
SS
will be clamped by the internal
forward biased diodes of the ADN2860.
V
DD
W
B
V
SS
Figure 16. Maximum Terminal Voltages Set by V
DD
& V
SS
The ground pin of the ADN2860 device is primarily used as a
digital ground reference, which needs to be tied to the common
ground of the PCB. The digital input control signals to the
ADN2860 must be referenced to the device ground pin, and
satisfy the logic levels defined in the specification table of this
datasheet.
An internal level shift circuit insures that the common mode
voltage range of the 2-terminals extends from V
SS
to V
DD
REV. PrD
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