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參數(shù)資料
| 型號(hào)： | ADS1194CZXGT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封裝： | 8 X 8 MM, GREEN, PLASTIC, NFBGA-64 |
| 文件頁數(shù)： | 22/76頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | ADS1194CZXGT |
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DRDY
DOUT
SCLK
Bit151
Bit150
Bit149
GPIOPin
GPIOData(read)
GPIOData(write)
GPIOControl
SBAS471B
– APRIL 2010 – REVISED APRIL 2011
Data Ready (DRDY)
DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the
data ready signal. The behavior of DRDY is determined by whetehr the device is in RDATAC mode or the
RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and
RDATA: Read Data subsections of the SPI command Definitions sections for further detials).When reading data
with the RDATA command, the read operation can overlap the occurrence of the next DRDY without data
corruption. The START pin or the START command is used to place the device either in normal data capture
mode or pulse data capture mode. Figure 29 shows the relationship between DRDY, DOUT, and SCLK during
data retrieval (in case of an ADS1198). DOUT is latched at the rising edge of SCLK. DRDY is pulled high at the
falling edge of SCLK. Note that DRDY goes high on the first falling edge SCLK regardless of whether data are
being retrieved from the device or a command is being sent through the DIN pin.
Figure 29. DRDY with Data Retrieval (CS = 0 in RDATA Mode)
GPIO
The ADS1194/6/8 have a total of four general-purpose digital I/O (GPIO) pins available in the normal mode of
operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits
register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the
data returned are the level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is
configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a
write to the GPIOD bit sets the output value.
If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on
or after a reset. Figure 30 shows the GPIO port structure.
GPIO1 can be used as the PACEIN signal; GPIO2 is multiplexed with RESP_BLK signal; GPIO3 is multiplexed
with the RESP signal; and GPIO4 is multiplexed with the RESP_PH signal.
Figure 30. GPIO Port Pin
Power-Down (PWDN)
When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin
high. Upon exiting from power-down mode, the internal oscillator and the reference require a wake-up time. It is
recommended that during power-down the external clock is shut down to save power.
Copyright
2010–2011, Texas Instruments Incorporated
29
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| ADS1194IPAG | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low-Power 8-Channel 16-Bit Analog Front-End for Biopotential Measurements |
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| ADS1196CPAG | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Pwr6Ch16B Ana Front-End for ECG RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1196CPAG | 制造商:Texas Instruments 功能描述:; Resolution (Bits):16bit; Sampling Rate 制造商:Texas Instruments 功能描述:IC, ADC, 6CH, 16BIT, 8KSPS, TQFP-64 |
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