參數(shù)資料
型號(hào)： ADS1194CZXGT
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PBGA64
封裝： 8 X 8 MM, GREEN, PLASTIC, NFBGA-64
文件頁(yè)數(shù)： 24/76頁(yè)
文件大?。?/td> 1193K
代理商： ADS1194CZXGT
STAR
co
TOp
de
STARTPin
DN
I
4/f
CLK
DRDY
or
t
SETTLE
t
DR
SBAS471B
– APRIL 2010 – REVISED APRIL 2011
Reset (RESET)
There are two methods to reset the ADS1194/6/8: pull the RESET pin low, or send the RESET opcode
command. When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width
timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth
SCLK falling edge of the opcode command. On reset it takes 18 CLK cycles to complete initialization of the
configuration registers to the default states and start the conversion cycle. Note that an internal RESET is
automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to a new value with a
WREG command.
START
The START pin must be set high, or the START command sent, to begin conversions. When START is low, or if
the START command has not been sent, the device does not issue a DRDY signal (conversions are halted).
When using the START opcode to control conversion, hold the START pin low. The ADS1194/6/8 feature two
modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT
(bit 3 of the CONFIG4 register). In multiple device configurations the START pin is used to synchronize devices
(see the Multiple Device Configuration subsection of the SPI Interface section for more details).
Settling Time
The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when START signal is
pulled high. Once START is pulled high, DRDY is also pulled high. The next falling edge of DRDY indicates that
data are ready. Figure 31 shows the timing diagram and Table 7 shows the settling time for different data rates.
The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1
register). Table 6 describes the settling time as a function of tCLK. Note that when START is held high and there
is a step change in the input signal, it takes 3
× tDR for the filter to settle to the new value. Settled data are
available on the fourth DRDY pulse. This time must be considered when trying to measure narrow pace pulses
for pacer detection.
Figure 31. Settling Time
Table 7. Settling Time for Different Data Rates
DR[2:0]
SETTLING TIME
UNIT
000
1160
tCLK
001
2312
tCLK
010
4616
tCLK
011
9224
tCLK
100
18440
tCLK
101
36872
tCLK
110
73736
tCLK
30
Copyright
2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS1194 ADS1196 ADS1198
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