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參數(shù)資料
| 型號： | ADSP-21061LASZ-176 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 240MQFP |
| 產(chǎn)品培訓模塊： | SHARC Processor Overview |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 同步串行端口（SSP） |
| 時鐘速率： | 44MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應商設備封裝： | 240-MQFP-EP（32x32） |
| 包裝： | 托盤 |
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Rev. D | Page 20 of 52 | May 2013
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed below may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD CAUTION
PACKAGE MARKING INFORMATION
The information presented in Figure 8 provides details about
the package branding for the ADSP-21061 processor. For a
complete listing of product availability, see Ordering Guide on
TIMING SPECIFICATIONS
The timing specifications shown are based on a CLKIN fre-
quency of 50 MHz (tCK = 20 ns). The DT derating enables the
calculation of timing specifications within the min to max range
between the derated CLKIN period (tCK) and a CLKIN period of
25 ns:
DT = tCK – 20 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, you
cannot meaningfully add parameters to derive longer times.
For voltage reference levels, see Figure 29 under Test
Conditions.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices. (O/D) = Open Drain,
(A/D) = Active Drive.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Parameter
5 V
3.3 V
Supply Voltage (VDD)
–0.3 V to +7.0 V
–0.3 V to +4.6 V
Input Voltage
–0.5 V to VDD +0.5 V
Output Voltage Swing
–0.5 V to VDD +0.5 V
Load Capacitance
200 pF
Storage Temperature Range
–65C to +150C–65C to +150C
Lead Temperature (5 seconds)
280C280C
Junction Temperature Under Bias
130C130C
Figure 8. Typical Package Marking (Actual Marking Format May Vary)
Table 6. Package Brand Information
Brand Key
Field Description
t
Temperature Range
pp
Package Type
Z
Lead Free Option
ccc
See Ordering Guide
vvvvvv.x
Assembly Lot Code
n.n
Silicon Revision
yyww
Date Code
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
vvvvvv.x n.n
tppZccc
S
ADSP-21061
a
yyww country_of_origin
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