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參數(shù)資料
| 型號： | ADSP-21061LASZ-176 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 240MQFP |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | 同步串行端口（SSP） |
| 時鐘速率： | 44MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-MQFP-EP（32x32） |
| 包裝： | 托盤 |
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Rev. D | Page 43 of 52 | May 2013
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, CL, and the
load current, IL. This decay time can be approximated by the
following equation:
The output disable time tDIS is the difference between
the interval from when the reference signal switches to when the
output voltage decays V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and IL,
and with V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 27). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the ADSP-21061’s output voltage
and the input threshold for the device requiring the hold time. A
typical V will be 0.4 V. CL is the total bus capacitance (per data
line), and IL is the total leakage or three-state current (per data
line). The hold time will be tDECAY plus the minimum disable
time (i.e., tDATRWH for the write cycle).
Output Drive Characteristics
output drivers of the ADSP-21061 (5 V) and ADSP-21061L
(3 V). The curves represent the current drive capability and
switching behavior of the output drivers as a function of
resistive and capacitive loading.
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 28). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figure 31,
cally how output delays and holds vary with load capacitance.
(Note that this graph or derating does not apply to output dis-
able delays; see the previous section Output Disable Time under
Test Conditions.) The graphs of Figure 31, Figure 32, Figure 35,
and Figure 36 may not be linear outside the ranges shown.
Figure 27. Output Enable/Disable
PEXT
CL V
IL
---------------
=
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) - V
VOL (MEASURED) + V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
2.0V
1.0V
VOH (MEASURED)
VOL (MEASURED)
HIGH IMPEDANCE STATE.
TESTCONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V.
OUTPUT STOPS
DRIVING
tENA
tDECAY
Figure 28. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
Figure 29. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
1.5V
50pF
TO
OUTPUT
PIN
IOL
IOH
INPUT
OR
OUTPUT
1.5V
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