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參數(shù)資料
| 型號： | ADSP-2115BPZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 19 |
| 系列： | ADSP-21xx |
| 類型： | 定點(diǎn) |
| 接口： | 同步串行端口（SSP） |
| 時鐘速率： | 25MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 3kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
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ADSP-21xx
–10–
REV. B
Figure 5. ADSP-2111 System
The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the
chip is configured for booting, with MMAP = 0). The first
instruction is then fetched from internal program memory
location 0x0000.
Program Memory Interface
The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single
external data bus and a single external address bus. The external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
The external address bus is 14 bits wide. For the ADSP-2101,
ADSP-2103, and ADSP-2111, these lines can directly address
up to 16K words, of which 2K are on-chip. For the ADSP-2105
and ADSP-2115, the address lines can directly address up to
15K words, of which 1K is on-chip.
The data lines are bidirectional. The program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. The write (WR) signal indicates a
write operation and is used as a write strobe. The read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
The ADSP-21xx processors write data from their 16-bit
registers to 24-bit program memory using the PX register to
provide the lower eight bits. When the processor reads 16-bit
data from 24-bit program memory to a 16-bit data register, the
lower eight bits are placed in the PX register.
The program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET
.
Program Memory Maps
Program memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 6 shows the two program
memory maps for the ADSP-2101, ADSP-2103, and
ADSP-2111. Figure 8 shows the program memory maps for the
ADSP-2105 and ADSP-2115. Figures 7 and 9 show the
program memory maps for the ADSP-2161/62 and ADSP-2163/
64, respectively.
BR
BG
CLKIN
RESET
IRQ2
BMS
CLKOUT
ADDR
DATA
(OPTIONAL)
1x CLOCK
or
CRYSTAL
PMS
DMS
RD
WR
ADDR
13-0
DATA
23-0
ADDR
DATA
(OPTIONAL)
ADDR
DATA
BOOT
MEMORY
e.g. EPROM
2764
27128
27256
27512
PROGRAM
MEMORY
DATA
MEMORY
&
PERIPHERALS
14
24
D
23-22
A
13-0
D
15-8
D
23-0
D
23-8
A
13-0
A
13-0
XTAL
MMAP
SERIAL
DEVICE
(OPTIONAL)
SCLK1
RFS1
or IRQ0
TFS1
or IRQ1
DT1
or FO
DR1
or FI
SPORT 1
SCLK0
RFS0
TFS0
DT0
DR0
SPORT 0
SERIAL
DEVICE
(OPTIONAL)
OE
WE
CS
OE
WE
CS
OE
CS
ADSP-2111
HOST
PROCESSOR
(OPTIONAL)
HOST INTERFACE PORT
CONTROL
DATA / ADDR
(OPTIONAL)
FL0
FL1
FL2
7
16
THE TWO MSBs OF THE DATA BUS (D
23-22
) ARE USED TO SUPPLY THE TWO MSBs OF THE
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
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