參數(shù)資料
型號: ADSP-2186LBSTZ-160
廠商: Analog Devices Inc
文件頁數(shù): 26/48頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 100LQFP
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機接口,串行端口
時鐘速率: 40MHz
非易失內存: 外部
芯片上RAM: 40kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
Rev. C
|
Page 32 of 48
|
January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
IDMA Write, Long Write Cycle
Table 22. IDMA Write, Long Write Cycle
Parameter
Min
Max
Unit
Timing Requirements:
tIKW
IACK Low Before Start of Write1
0ns
tIKSU
IAD15 – 0 Data Setup Before End of Write2, 3, 4
0.5tCK + 10
ns
tIKH
IAD15–0 Data Hold After End of Write2, 3, 4
2ns
Switching Characteristics:
tIKLW
Start of Write to IACK Low
1.5tCK
ns
tIKHW
Start of Write to IACK High
5
17
ns
1 Start of Write = IS Low and IWR Low.
2 If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
3 If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.
5 For the ADSP-2185L, and the ADSP-2187L, this specification is 4 ns min., and 15 ns max.
Figure 24. IDMA Write, Long Write Cycle
IAD15–0
DATA
tIKHW
t
IK W
IACK
IS
IWR
tIKLW
tIKH
t
IK SU
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