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| 型號： | ADSP-2186LBSTZ-160 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 40MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 40kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C
|
Page 17 of 48
|
January 2008
PIN DESCRIPTIONS
ADSP-218xL series members are available in a 100-lead LQFP
package and a 144-ball BGA package. In order to maintain max-
imum functionality and reduce package size and pin count,
some serial port, programmable flag, interrupt and external bus
pins have dual, multiplexed functionality. The external bus pins
are configured during RESET only, while serial port pins are
software configurable during program execution. Flag and
interrupt functionality is retained concurrently on multiplexed
pins. In cases where pin functionality is reconfigurable, the
default state is shown in plain text in Table 9, while alternate
functionality is shown in italics.
Table 9. Common-Mode Pins
Pin Name
No. of Pins
I/O
Function
RESET
1
I
Processor Reset Input
BR
1I
Bus Request Input
BG
1
O
Bus Grant Output
BGH
1
O
Bus Grant Hung Output
DMS
1
O
Data Memory Select Output
PMS
1
O
Program Memory Select Output
IOMS
1
O
Memory Select Output
BMS
1
O
Byte Memory Select Output
CMS
1
O
Combined Memory Select Output
RD
1
O
Memory Read Enable Output
WR
1
O
Memory Write Enable Output
IRQ2/
1
I
Edge- or Level-Sensitive Interrupt Request1
PF7
I/O
Programmable I/O Pin
IRQL1/
1
I
Level-Sensitive Interrupt Requests
PF6
I/O
Programmable I/O Pin
IRQL0/
1
I
Level-Sensitive Interrupt Requests
PF5
I/O
Programmable I/O Pin
IRQE/
1
I
Edge-Sensitive Interrupt Requests1
PF4
I/O
Programmable I/O Pin
Mode D
2/
1
I
Mode Select Input—Checked Only During RESET
PF3
I/O
Programmable I/O Pin During Normal Operation
Mode C/
1
I
Mode Select Input—Checked Only During RESET
PF2
I/O
Programmable I/O Pin During Normal Operation
Mode B/
1
I
Mode Select Input—Checked Only During RESET
PF1
I/O
Programmable I/O Pin During Normal Operation
Mode A/
1
I
Mode Select Input—Checked Only During RESET
PF0
I/O
Programmable I/O Pin During Normal Operation
CLKIN
1
I
Clock Input
XTAL
1
O
Quartz Crystal Output
CLKOUT
1
O
Processor Clock Output
SPORT0
5
I/O
Serial Port I/O Pins
SPORT1/
5
I/O
Serial Port I/O Pins
IRQ1 – 0, FI, FO
Edge- or Level-Sensitive Interrupts, FI, FO
3
PWD
1
I
Power-Down Control Input
PWDACK
1
O
Power-Down Acknowledge Control Output
FL0, FL1, FL2
3
O
Output Flags
VDDINT
2I
Internal VDD (1.8 V) Power (LQFP)
VDDEXT
4I
External VDD (1.8 V, 2.5 V, or 3.3 V) Power (LQFP)
GND
10
I
Ground (LQFP)
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