mode only. In 0-to-VREF mode (with V
參數(shù)資料
型號(hào)： ADUC7023BCP6Z62IRL
廠商： Analog Devices Inc
文件頁數(shù)： 40/96頁
文件大?。?/td> 0K
描述： IC MCU 12BIT 62KB FLASH 40LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： I²C，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12 x12b; D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7023
| Page 45 of 96
mode only. In 0-to-VREF mode (with VREF < AVDD), the lower
nonlinearity is similar. However, the upper portion of the transfer
function follows the ideal line right to the end (VREF in this case,
not AVDD), showing no signs of endpoint linearity errors.
08675-
027
AVDD
AVDD – 100mV
100mV
0x00000000
0x0FFF0000
Figure 33. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 33
get worse as a function of output loading. Most of the ADuC7023
data sheet specifications assume a 5 k resistive load to ground
at the DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom of Figure 33
become larger, respectively. With larger current demands, this
can significantly limit output voltage swing.
References to ADC and the DACs
ADC and DACs can be configured to use internal VREF or an
external reference as a reference source. Internal VREF must
work with an external 0.47 F capacitor. Note that if an external
reference is used, the DACs will no longer meet offset and gain
specifications. If an external reference is required for the ADC,
then the DACs should be configured to use the 0 to AVDD range.
Table 42. Reference Source Selection for ADC and DAC
REFCON Bit 0
DACxCON[1:0]
Description
0
00
ADC works with external
reference. DACs power down.
0
01
Reserved.
0
10
Reserved.
0
11
ADC works with external
reference. DACs work with
internal AVDD.
1
00
ADC works with internal
VREF. DACs power down.
1
01
ADC and DACs work with an
external reference. The
external reference must be
capable of overdriving the
internal reference.
1
10
ADC and DACs work with
internal VREF
1
11
ADC works with internal VREF.
DACs work with internal AVDD.
Configuring DAC Buffers in Op Amp Mode
In op amp mode, the DAC output buffers are used as an op amp
with the DAC itself disabled.
If DACBCFG Bit 0 is set, ADC0 is the positive input to the op
amp, ADC1 is the negative input, and DAC0 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC0CON.
If DACBCFG Bit 1 is set, ADC2 is the positive input to the op
amp, ADC3 is the negative input, and DAC1 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC1CON.
If DACBCFG Bit 2 is set, ADC4 is the positive input to the op
amp, ADC5 is the negative input, and DAC2 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC2CON.
If DACBCFG Bit 3 is set, ADC8 is the positive input to the op
amp, ADC9 is the negative input, and DAC3 is the output. In
this mode, the DAC should be powered down by clearing Bit 0
and Bit 1 of DAC3CON.
DACBCFG Register
Name:
DACBCFG
Address:
0xFFFF0654
Default value:
0x00
Access:
Read/write
Table 43. DACBCFG MMR Bit Designations
Bit
Description
7 to 4
Reserved. Always set to 0.
3
This bit is set to 1 to configure DAC3 output
buffer in op amp mode.
This bit is cleared for the DAC buffer to operate
as normal.
2
This bit is set to 1 to configure DAC2 output
buffer in op amp mode.
This bit is cleared for the DAC buffer to operate
as normal.
1
This bit is set to 1 to configure DAC1 output
buffer in op amp mode.
This bit is cleared for the DAC buffer to operate
as normal.
0
This bit is set to 1 to configure DAC0 output
buffer in op amp mode.
This bit is cleared for the DAC buffer to operate
as normal.
Rev. E
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