參數(shù)資料
型號(hào)： ADUC7023BCP6Z62IRL
廠商： Analog Devices Inc
文件頁數(shù)： 87/96頁
文件大小： 0K
描述： IC MCU 12BIT 62KB FLASH 40LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： I²C，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12 x12b; D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7023
Data Sheet
| Page 88 of 96
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7023 operational power supply voltage range is 2.7 V
to 3.6 V. Separate analog and digital power supply pins (AVDD
and IOVDD, respectively) allow AVDD to be kept relatively free of
noisy digital signals often present on the system IOVDD line. In
this mode, the part can also operate with split supplies, that is, it
can use different voltage levels for each supply. For example, the
system can be designed to operate with an IOVDD voltage level
of 3.3 V while the AVDD level can be at 3 V, or vice versa. A
typical split supply configuration is shown in Figure 46.
08675-
041
ADuC7023
IOVDD
AVDD
GNDREF
AGND
IOGND
0.1F
10F
DIGITAL SUPPLY
ANALOG SUPPLY
Figure 46. External Dual Supply Connections
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series resistor
and/or ferrite bead between AVDD and IOVDD, and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 47. With this configuration, other analog circuitry
(such as op amps, voltage reference, and others) can be powered
from the AVDD supply line as well.
08675-
054
ADuC7023
IOVDD
AVDD
GNDREF
AGND
REFGND
IOGND
0.1F
1.6V
10F
0.1F
DIGITAL SUPPLY
BEAD
10F
Figure 47. External Single Supply Connections
In both Figure 46 and Figure 47, a large value (10 F) reservoir
capacitor sits on IOVDD, and a separate 10 F capacitor sits on
AVDD. In addition, local small-value (0.1 F) capacitors are located
at each AVDD and IOVDD pin of the chip. As per standard design
practice, include all of these capacitors and ensure the smaller
capacitors are close to each AVDD pin with trace lengths as
short as possible. Connect the ground terminal of each of
these capacitors directly to the underlying ground plane.
Finally, the analog and digital ground pins on the ADuC7023
must be referenced to the same system ground reference point
at all times.
IOVDD Supply Sensitivity
The IOVDD supply is sensitive to high frequency noise because it
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature is
to ensure that no flash interface timings or ARM7TDMI
timings are violated.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
If decoupling values recommended in the Power Supplies section
do not sufficiently dampen all noise soures below 50 mV on IOVDD,
a filter such as the one shown in Figure 48 is recommended.
08675-
042
ADuC7023
IOVDD
IOGND
0.1F
10F
1H
DIGITAL
SUPPLY
Figure 48. Recommended IOVDD Supply Filter
Linear Voltage Regulator
Each ADuC7023 requires a single 3.3 V supply, but the core
logic requires a 2.6 V supply. An on-chip linear regulator generates
the 2.6 V from IOVDD for the core logic. The LVDD pin is the 2.6 V
supply for the core logic. An external compensation capacitor of
0.47 F must be connected between LVDD and DGND (as close
as possible to these pins) to act as a tank of charge, as shown in
08675-
043
ADuC7023
LVDD
DGND
0.47F
Figure 49. Voltage Regulator Connections
The LVDD pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOVDD to help improve line regulation performance of the
on-chip voltage regulator.
Rev. E
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