參數(shù)資料
型號： ADUC7023BCP6Z62IRL
廠商： Analog Devices Inc
文件頁數(shù)： 8/96頁
文件大小： 0K
描述： IC MCU 12BIT 62KB FLASH 40LFCSP
標準包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： I²C，SPI
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12 x12b; D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7023
Data Sheet
| Page 16 of 96
Pin No.
40-
LFCSP
32-
LFCSP
36-
WLCSP
Mnemonic
Description
28
24
C3
P0.3/PLAO[9]/TCK
The default value of this pin depends on the level of P0.0/BM. If P0.0/BM =
0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin
defaults to a JTAG test data clock pin. This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.3.
Programmable Logic Array Output Element 9.
Test Clock, JTAG Test Port Clock Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed.
17
13
E3
DGND
Digital Ground.
18
14
F3
IOVDD
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
19
15
D3
LVDD
2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 F capacitor to DGND only.
20
16
F2
RST
Reset Input, Active Low.
23
19
E1
RTCK
Return JTAG Clock Signal. This is not the standard JTAG clock signal. It is
an output signal from the JTAG controller. If using a 20-lead JTAG header,
connect to Pin 11.
9
7
F6
P0.4/IRQ0/SCL0/PLAI[0]/CONV
General-Purpose Input and Output Port 0.4/External Interrupt Request 0/ I2C0
Clock Signal/Programmable Logic Array Input Element 0/ADC External
Convert Start. By default, this pin is configured as a digital input with a
weak pull-up resistor enabled.
10
8
E5
P0.5/SDA0/PLAI[1]/COMPOUT
General-Purpose Input and Output Port 0.5/I2C0 Data Signal/ Programmable
Logic Array Input Element 1/Voltage Comparator Output. By default, this
pin is configured as a digital input with a weak pull-up resistor enabled.
11
9
F5
P0.6/MISO/SCL1/PLAI[2]
General-Purpose Input and Output Port 0.6/SPI MISO Signal/I2C1 Clock On
32-Lead and 36-Ball Packages/Programmable Logic Array Input Element 2.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
12
10
D4
P0.7/MOSI/SDA1/PLAO[0]
General-Purpose Input and Output Port 0.7/SPI MOSI Signal/I2C1 Data
Signal On 32-Lead and 36-Ball Packages/Programmable Logic Array Output
Element 0.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
21
17
F1
XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits. Connect to DGND if unused.
22
18
E2
XCLKO
Output from the Crystal Oscillator Inverter. Leave unconnected if unused.
16
N/A
P1.7/PWM3/SDA1/PLAI[6]
General-Purpose Input and Output Port 1.7/PWM Output 3/I2C1 Data
Signal/Programmable Logic Array Input Element 6. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
15
N/A
P1.6/PWM2/SCL1/PLAI[5]
General-Purpose Input and Output Port 1.6/PWM Output 2/I2C1 Clock
Signal/Programmable Logic Array Input Element 5. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
29
N/A
P1.5/ADC6/PWMTRIPINPUT/PLAO[4]
General-Purpose Input and Output Port 1.5/ADC Single-Ended or
Differential Analog Input 6/PWMTRIPINPUT/Programmable Logic Array Output
Element 4. By default, this pin is configured as a digital input with a weak
pull-up resistor enabled. When used as ADC input, the pull-up resistor
should be disabled manually.
7
N/A
P1.4/ADC10/PLAO[3]
General-Purpose Input and Output Port 1.4/ADC Single-Ended or Dif-
ferential Analog Input 10/Programmable Logic Array Output Element 3.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
Rev. E
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