參數(shù)資料
型號： ADUC7060BCPZ32-RL
廠商： Analog Devices Inc
文件頁數(shù)： 24/108頁
文件大?。?/td> 0K
描述： IC MCU FLASH 24BIT 32KB 48LFCSP
設(shè)計資源： 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Low power, Long Range, ISM Wireless Measuring Node (CN0164)
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 14
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 22 of 108
such as C, it is necessary to ensure that the stack does not overflow.
This is dependent on the performance of the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
in Figure 9. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_UND
SPSR_IRQ
SPSR_ABT
SPSR_SVC
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_UND
R14_UND
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
R13_IRQ
R14_IRQ
R13_ABT
R14_ABT
R13_SVC
R14_SVC
SPSR_FIQ
CPSR
USER MODE
FIQ
MODE
SVC
MODE
ABORT
MODE
IRQ
MODE
UNDEFINED
MODE
07079-
004
Figure 9. Register Organization
INTERRUPT LATENCY
The worst-case latency for an FIQ consists of the longest time
that the request can take to pass through the synchronizer, plus
the time for the longest instruction to complete (the longest
instruction is an LDM) that loads all the registers including the
PC, plus the time for the data abort entry, plus the time for FIQ
entry. At the end of this time, the ARM7TDMI is executing the
instruction at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, or just over 4.88 μs in a system
using a continuous 10.24 MHz processor clock. The maximum
IRQ latency calculation is similar but must allow for the FIQ
having higher priority, which can delay entry into the IRQ
handling routine for an arbitrary length of time. This time can be
reduced to 42 cycles if the LDM command is not used; some
compilers have an option to compile without using this command.
Another option is to run the part in Thumb mode where this
time is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time that the request can take through
the synchronizer plus the time to enter the exception mode.
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if required,
for example, when executing interrupt service routines.
MEMORY ORGANIZATION
The ARM7, a von Neumann architecture MCU core, sees
memory as a linear array of 232-byte locations. As shown in
Figure 10, the ADuC706x maps this into four distinct user
areas: a memory area that can be remapped, an SRAM area, a
Flash/EE area, and a memory mapped register (MMR) area.
The first 30 kB of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped. Any
access, either reading or writing, to an area not defined in the
memory map results in a data abort exception.
Memory Format
The ADuC706x memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address (see Figure 11).
0x00040FFF
0x00040000
0xFFFFFFFF
0xFFFF0000
MMRs
0x00087FFF
0x00080000
FLASH/EE
SRAM
0x00007FFF
0x00000000
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
RESERVED
07079-
005
Figure 10. Memory Map
BIT 31
BYTE 2
A
6
2
.
BYTE 3
B
7
3
.
BYTE 1
9
5
1
.
BYTE 0
8
4
0
.
BIT 0
32 BITS
0xFFFFFFFF
0x00000004
0x00000000
07079-
006
Figure 11. Little Endian Format
SRAM
The ADuC706x features 4 kB of SRAM, organized as 1024 ×
32 bits, that is, 1024 words located at 0x40000. The RAM space
can be used as data memory as well as volatile program space.
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide memory
array. SRAM is read/writable in 8-, 16-, and 32-bit segments.
Remap
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
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ADUC70SMARTLINKRL7 制造商:Analog Devices 功能描述:
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